3D Semiconductor Interconnection Structure for High Integration
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Solution Overview
Problem
Two-dimensional semiconductor memory devices face limitations in cost savings due to the need for high-priced equipment for forming fine patterns, which restricts the ability to increase the degree of integration and reduce costs.
Innovation Solution
A three-dimensional semiconductor device with stacked layers of word lines and interconnection layers, where the pitch of word line groups and interconnections are optimized to minimize space and reduce the number of word lines sharing the same layer, allowing for increased integration without compromising reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor memory devices are used to increase degree of integration, then more high-priced equipment is required for forming fine patterns, but cost savings are limited
Solution Approach 1:
The patent transitions from a two-dimensional planar memory structure to a three-dimensional stacked structure with multiple layers of word lines and interconnection layers. This dimensional change allows increased integration density without requiring proportionally more complex patterning equipment, as the vertical stacking provides additional space for memory cells and interconnections.
2Quantity of substance
If the number of word lines is increased in stacked structures, then degree of integration is enhanced, but crosstalk between adjacent word lines increases
Solution Approach 1:
The patent divides word lines into multiple groups across different stacked layers, with each group connected to separate interconnection layers. This segmentation isolates adjacent word lines in the vertical dimension, reducing capacitive coupling and crosstalk while allowing a higher total number of word lines to be implemented.
Solution Approach 2:
The patent introduces intermediate interconnection layers between stacked word line structures. These intermediate layers act as mediators that electrically connect to specific groups of word lines, providing isolation and reducing direct interference between adjacent word line groups in the vertical stacking direction.
3Area of stationary object
If pitch of word line groups is reduced to minimize space, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes vertical stacking to accommodate multiple word line groups, allowing the horizontal pitch between adjacent groups to be reduced while maintaining adequate separation through the vertical dimension. The multi-layer interconnection structure provides additional routing space that compensates for reduced horizontal pitch.
Solution Approach 2:
The patent implements a nested structure where multiple word line groups are stacked vertically with interconnection layers interleaved between them. This nesting arrangement allows compact horizontal spacing while maintaining electrical isolation and reducing the overall footprint area without excessively tightening the pitch control requirements.
Data Source
AI summary
A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.