3D Semiconductor Device With Laser Annealing And Heat Spreading
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Solution Overview
Problem
In 3D stacked integrated circuits, the degradation of wire performance with 'scaling' and the challenge of heat removal due to increased power density, along with the damage to lattice structures and underlying devices from high-temperature thermal treatments, hinder the development of efficient and reliable multilayer IC devices.
Innovation Solution
Incorporating a heat spreading and conducting material layer, such as a shield/heat sink layer, between sensitive metal interconnect layers and the regions being annealed, and using optical annealing techniques like laser annealing to repair defects and activate dopants without damaging underlying metal layers, thereby maintaining low effective temperatures and improving heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-temperature thermal treatments are used to repair lattice structures, then crystal lattice defects are reduced, but underlying metal interconnect layers and device layers are damaged
Solution Approach 1:
The patent segments the treatment process by applying laser annealing selectively to specific regions requiring crystal lattice repair, rather than uniformly heating the entire wafer. This localized approach repairs defects in the semiconductor layer while limiting thermal exposure to underlying metal interconnect layers, thus resolving the contradiction between improving crystal quality and preventing thermal damage.
Solution Approach 2:
The patent introduces an intermediary protective layer or process control mechanism that mediates between the heat source and the metal interconnect layers. This intermediary allows sufficient heat to reach the semiconductor layer for defect repair while blocking or dissipating excessive heat before it damages the metal interconnects, thereby resolving the thermal damage issue while maintaining lattice quality improvement.
2Speed
If 3D stacking is implemented to reduce wire lengths, then wiring delay is reduced, but heat removal becomes more difficult due to increased power density
Solution Approach 1:
The patent applies local quality by implementing region-specific thermal management strategies in the 3D stacked structure. Different areas of the device receive differentiated cooling approaches based on their power density and thermal requirements, allowing efficient heat removal from high-power regions while maintaining the compact 3D architecture that reduces wiring delay.
Solution Approach 2:
The patent utilizes another dimension by introducing vertical thermal management pathways in the 3D stacked structure. Heat is conducted and removed through the vertical dimension via thermally conductive vias and heat sink layers positioned at different stacking levels, enabling effective heat dissipation from densely packed transistor layers without compromising the horizontal wiring benefits of 3D stacking.
3Object-affected harmful factors
If optical annealing is used to maintain low effective temperatures, then metal interconnect layers are protected, but the annealing effectiveness is reduced compared to high-temperature thermal treatment
Solution Approach 1:
The patent employs periodic action by using pulsed or cyclic optical annealing sequences. Multiple short-duration laser pulses are applied in succession, each delivering controlled energy to accumulate the necessary thermal effect for defect repair while allowing cooling intervals that prevent excessive temperature buildup. This periodic approach maintains annealing effectiveness equivalent to high-temperature treatment while protecting metal interconnect layers from thermal damage.
Solution Approach 2:
The patent applies parameter changes by optimizing multiple variables of the optical annealing process, including laser wavelength, pulse duration, power density, and scanning speed. By carefully adjusting these parameters, the process achieves sufficient thermal energy delivery for crystal lattice repair while maintaining the effective temperature below the damage threshold for metal interconnect layers, thus resolving the contradiction between annealing effectiveness and thermal protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of defect-free crystalline semiconductor layers at low temperatures, reduces thermal damage to metal interconnects, and enhances heat removal efficiency in 3D ICs, improving device performance and yield.
Implementation Method 1
illuminating the semiconductor layer with a laser or other optical beam to heat and anneal the semiconductor layer
Implementation Method 2
optical annealing techniques like laser annealing to repair defects and activate dopants
Data Source
AI summary
A semiconductor device including: a silicon layer including a single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level and has a diameter of less than 450 nm, where the second level thickness is less than four microns, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.