3D Semiconductor Substrate Layout for Heat and Signal Delay Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving both high functionality and cost reduction, particularly in image sensors with three-dimensional structures, due to limitations in mountable circuit area, increased costs, heat generation, and signal delays from close circuit arrangements.
Innovation Solution
A semiconductor device with a three-dimensional structure is designed, featuring multiple stacked semiconductor layers mounted at positions requiring large circuit areas and single-layer structures where space is limited, utilizing CuCu bonding for electrical connections, allowing flexible circuit placement and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple circuit chips are mounted side by side on the back surface to increase functionality, then the mountable circuit area is increased, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The back surface is divided into multiple mounting regions where different circuit chips can be selectively mounted. Each region corresponds to a specific functional area, allowing independent mounting decisions for each chip type and quantity, thereby increasing functionality while maintaining manageable complexity through modular segmentation
Solution Approach 2:
The patent transitions from single-layer mounting to multi-layer stacked mounting, utilizing the vertical dimension (thickness direction) to mount circuit chips. This three-dimensional arrangement increases the effective mountable area without expanding the planar footprint, thereby enhancing functionality while controlling device complexity through spatial optimization
2Adaptability or versatility
If circuit chips are mounted close together to increase functionality, then the device size is reduced, but heat generation increases and signal delays occur
Solution Approach 1:
By utilizing the thickness direction for multi-layer stacking, the patent distributes circuit chips vertically across multiple layers rather than crowding them horizontally. This three-dimensional arrangement maintains compact device size while increasing spacing between adjacent chips in the planar direction, thereby reducing heat generation and signal delays while preserving high functionality
Solution Approach 2:
The back surface is segmented into multiple mounting regions corresponding to different functional areas. This segmentation allows strategic placement of heat-generating chips in regions with better thermal management capabilities and enables independent thermal design for each functional block, reducing overall heat generation while maintaining high functionality
3Adaptability or versatility
If multiple semiconductor layers are stacked to increase functionality, then the circuit integration is improved, but the manufacturing cost increases
Solution Approach 1:
The patent enables selective mounting where circuit chips are mounted only in specific regions and layers based on functional requirements. This partial action approach allows manufacturers to produce different device configurations from the same substrate structure, achieving high functionality where needed while reducing manufacturing complexity and cost in less critical areas
Solution Approach 2:
The substrate structure with multiple mounting regions and stacked layers serves multiple functions: it provides mechanical support, electrical connections, thermal management pathways, and flexible mounting configurations. This multi-functionality reduces the need for additional specialized components and processes, thereby controlling manufacturing cost while achieving high functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves high functionality while reducing costs and minimizing heat generation and signal delays, while also enabling efficient manufacturing with reduced power consumption and improved reliability.
Implementation Method 1
utilizing CuCu bonding for electrical connections
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor device according to one embodiment of the present disclosure includes a first substrate, a second substrate, and a third substrate. The first substrate has a first surface and a second surface that are opposed to each other. The first substrate includes a plurality of semiconductor elements formed on a side of the first surface. The second substrate is mounted on the second surface of the first substrate. The second substrate includes a plurality of semiconductor layers being stacked. The plurality of semiconductor layers each include one or a plurality of circuits. The third substrate is mounted side by side to the second substrate on the second surface of the first substrate. The third substrate includes one or a plurality of semiconductor layers being stacked. The one or the plurality of semiconductor layers each include one or a plurality of circuits.