3D Semiconductor Device With Liner Layer For Uniform Transistors
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Solution Overview
Problem
The integration limits of two-dimensional nonvolatile memory devices necessitate the development of three-dimensional semiconductor devices with vertically stacked memory cells, requiring uniform selection transistor characteristics for improved operation and reliability.
Innovation Solution
A semiconductor device structure featuring alternately stacked conductive and insulating layers, with a liner layer interposed between semiconductor layers and protruding through a capping layer, and a method of manufacturing that includes laser recrystallization to form uniform semiconductor layers and doping for consistent transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two-dimensional nonvolatile memory devices are integrated in a single layer on a substrate, then the manufacturing process is simple, but the integration density reaches its physical limit
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked along the vertical direction, with channel layers extending through multiple interlayer insulating layers and gate electrodes, thereby increasing integration density by utilizing the third dimension (vertical stacking) rather than expanding only in the planar direction
2Productivity
If three-dimensional memory devices with vertically stacked memory cells are implemented, then integration density is improved, but uniform characteristics of selection transistors become difficult to achieve
Solution Approach 1:
The patent introduces a liner layer with specific material properties (different from both the first and second semiconductor layers) positioned at the interface between the first semiconductor layer and the second semiconductor layer. This liner layer has distinct etch selectivity and physical properties that locally modify the interface characteristics, ensuring uniform formation of the second semiconductor layer and consistent transistor properties across the three-dimensional structure
Solution Approach 2:
The liner layer acts as an intermediary layer between the first semiconductor layer and the second semiconductor layer. It facilitates the formation process by providing a controlled interface that enables precise deposition or growth of the second semiconductor layer, thereby ensuring uniform thickness and electrical characteristics of the channel layers in the vertically stacked memory cells
3Manufacturing precision
If laser recrystallization is used to form uniform semiconductor layers, then manufacturing precision is improved, but energy consumption increases
Solution Approach 1:
The patent employs laser recrystallization to transform the physical and chemical parameters of the semiconductor layers. By controlling laser parameters (energy density, pulse duration, scanning speed), the semiconductor layers are melted and recrystallized to achieve atomic-level uniformity in composition and crystal structure, thereby improving manufacturing precision through parameter optimization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of transistors with uniform properties, enhancing the operating characteristics and reliability of three-dimensional semiconductor devices by ensuring consistent channel layers and gate electrodes, thus improving the performance and stability of memory devices.
Implementation Method 1
a method of manufacturing that includes laser recrystallization to form uniform semiconductor layers
Data Source
AI summary
A semiconductor device includes alternately stacked conductive layers and the insulating layers, an opening passing through the conductive layers and insulating layers, a first semiconductor layer formed in the opening, a second semiconductor layer formed in the first semiconductor layer, a capping layer formed in the opening and disposed over the first semiconductor layer and the second semiconductor layer, and a liner layer interposed between the first semiconductor layer and the second semiconductor layer and protruding through the capping layer relative to the first semiconductor layer and the second semiconductor layer.