3D Semiconductor Memory Devices With Vertical Connecting Layer
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Solution Overview
Problem
Current 3D-IC memory fabrication processes, such as the punch-and-plug method, face challenges in efficiently increasing memory capacity without significant cost increases and in erasing memory cells using a simple bulk erase scheme.
Innovation Solution
A three-dimensional semiconductor device is fabricated using a method that includes forming conductive patterns on a substrate, penetrating semiconductor patterns, and using a semiconductor connecting layer to connect these patterns to the substrate, with memory elements interposed between the channel regions and conductive patterns, allowing for a bulk erase capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If punch-and-plug process is used to increase memory capacity, then memory capacity increases, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to three-dimensional vertical stacking, where memory cells are arranged in multiple layers along the vertical direction. This dimensional change allows significant increase in memory capacity without proportionally increasing manufacturing process complexity, as the basic fabrication steps can be repeated for each layer.
Solution Approach 2:
The memory device is divided into multiple stacked layers, each containing memory cells, conductive patterns, and insulating layers. This segmentation allows independent fabrication and optimization of each layer while maintaining overall system functionality, enabling capacity expansion through layer multiplication rather than complex monolithic structures.
2Quantity of substance
If complex fabrication process is used to achieve 3D structure, then memory capacity increases, but manufacturing cost increases drastically
Solution Approach 1:
The patent employs universal fabrication steps that can be repeatedly applied to create multiple identical layers. The same patterning, deposition, and etching processes are used for each memory cell layer, allowing standardization and economies of scale. This multi-functional approach enables cost-effective production of high-capacity 3D memory by avoiding custom complex processes for each layer.
3Ease of manufacture
If conventional erase scheme is used, then manufacturing is simple, but memory cell erasure efficiency is insufficient for 3D structure
Solution Approach 1:
The patent introduces a semiconductor connecting layer as an intermediary component that extends from the substrate through the vertical structure to connect with upper layers. This connecting layer serves as a mediator for applying erase voltages throughout the three-dimensional memory cell array, enabling efficient bulk erase operation while maintaining manufacturing simplicity by using standard semiconductor materials and processes.
Data Source
AI summary
Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.