3D Semiconductor Memory Layout with Compact Peripheral Circuits
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in optimizing the layout and configuration of memory cell arrays and peripheral circuits, leading to inefficiencies in data storage and retrieval operations.
Innovation Solution
A semiconductor memory device with a three-dimensional arrangement of memory cells, featuring a memory cell array and peripheral circuits optimized for reduced size and enhanced functionality, including a sense amplifier configuration that minimizes the second-direction length of the peripheral circuit to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the peripheral circuit is extended to provide enhanced functionality, then device functionality is improved, but device size increases
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture, placing memory cell arrays and peripheral circuits in vertical layers. This dimensional change allows enhanced functionality to be achieved without proportionally increasing the device footprint, as components are arranged in the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The patent implements a nested structure where peripheral circuits are positioned between the substrate and memory cell arrays, with additional peripheral circuits arranged in subsequent layers above the first layer. This nesting approach allows multiple functional blocks to be compactly integrated within a limited vertical space, maintaining small device size while providing enhanced functionality.
2Area of stationary object
If the second-direction length of the peripheral circuit is reduced, then device size is minimized, but circuit functionality may be compromised
Solution Approach 1:
By arranging peripheral circuits in the vertical dimension across multiple layers rather than extending them horizontally, the patent achieves compact device size in the planar view while maintaining complete circuit functionality through three-dimensional interconnection.
Solution Approach 2:
The peripheral circuit is divided into multiple segments distributed across different vertical layers. The first peripheral circuit is positioned between the substrate and memory cell arrays, while additional peripheral circuits are arranged in subsequent layers. This segmentation allows each segment to be compact in the horizontal direction while collectively providing full functionality through vertical integration.
Data Source
AI summary
A semiconductor memory device includes a memory array provided above a substrate in a first direction intersecting a surface of the substrate. A first peripheral circuit is provided between the substrate and the memory array. A second peripheral circuit is provided between the substrate and the memory array and apart from the first peripheral circuit in a second direction parallel to the surface of the substrate. First and second sense amplifiers are provided between the substrate and the memory cell array, and a word line switch circuit extending in the second direction is provided between the first and second sense amplifiers. A length of the second peripheral circuit in the second direction is smaller than half of a length of the first and second sense amplifiers in the second direction.