3D Semiconductor Memory Device Vertical Integration
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Solution Overview
Problem
Current two-dimensional semiconductor devices face limitations in integration density due to the fineness of pattern processing equipment, which restricts the reliability and integration of memory cells, while three-dimensional semiconductor memory devices aim to enhance these aspects but require innovative structural and manufacturing approaches to achieve higher reliability and integration.
Innovation Solution
A three-dimensional semiconductor memory device is designed with a stacked structure comprising a peripheral logic structure and a cell array structure, featuring vertically arranged memory cells, through via structures, and a unique electrode structure with ground select and cell gate electrodes, allowing for increased integration and reliability by optimizing the arrangement and connection of memory cells and logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional or planar semiconductor devices are used, then manufacturing cost is relatively low and manufacturing process is simpler, but integration density is limited due to pattern fineness constraints
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked memory cell structures. Multiple memory cell layers are stacked in the vertical direction, with through via structures penetrating through the stacked layers to provide electrical connections. This dimensional change enables significantly higher integration density without being constrained by pattern fineness of processing equipment.
2Quantity of substance
If three-dimensional semiconductor memory devices with vertically stacked structures are implemented, then integration density is increased, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The three-dimensional memory device is segmented into multiple distinct layers including first memory cell layers, second memory cell layers, insulating layers, and connection regions. Each layer has specific functions and can be processed independently to some extent. Through via structures are formed to penetrate through these segmented layers, enabling electrical connections while maintaining manufacturing feasibility through modular processing approaches.
Solution Approach 2:
Connection regions are introduced as intermediary structures between the stacked memory cell layers and peripheral circuit regions. These connection regions facilitate the formation of through via structures and provide transition zones for electrical connections, simplifying the overall manufacturing process by creating distinct functional zones that can be processed systematically.
3Area of stationary object
If memory cell layers are stacked vertically to increase integration density, then area occupation is reduced, but electrical connection complexity increases
Solution Approach 1:
Electrical connections are established in the vertical dimension through through via structures that penetrate through the stacked memory cell layers. This allows bit lines and word lines to access memory cells in different layers without requiring complex lateral routing, thereby reducing chip area occupation while managing connection complexity through vertical integration.
Solution Approach 2:
Insulating layers are positioned between adjacent memory cell layers to serve as intermediaries that provide electrical isolation. These insulating layers prevent unwanted electrical interactions between stacked layers while allowing controlled connections through the through via structures, thereby simplifying the electrical connection architecture.
Data Source
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Figure 3A
AI summary
A three-dimensional semiconductor memory device includes a peripheral logic structure on a semiconductor substrate. A horizontal semiconductor layer is on the peripheral logic structure and includes a cell array region and a connection region. Electrode structures extend in a first direction on the horizontal semiconductor layer and are spaced apart in a second direction intersecting the first direction. A pair of the electrode structures adjacent to each other are symmetrically disposed to define a contact region partially exposing the horizontal semiconductor layer. A through via structure is on the contact region and connects the electrode structures to the peripheral logic structure. Each of the electrode structures includes a plurality of gate insulation regions extending along the first direction on the connection region. The gate insulation regions have different lengths from each other in the first direction.