Solid-State Devices TRIZ Cases

Specific molecular structures reduce intermolecular aggregation to improve device stability and efficiency.

A vertical memory device uses a three-dimensional channel to connect gate electrodes and substrate regions.

Varying microlens heights via variable thickness photomasks to reduce light field curvature and improve image sensor photosensitivity.

Elevated conductive bodies allow salicide formation away from the substrate, reducing contact resistance while preventing metal contamination.

An inclined gallium nitride substrate dissipates heat through enhanced thermal conduction, allowing high-power operation without separate cooling systems.

Baking isolation layer surfaces before oxidation prevents impurity outgassing during gate dielectric formation.

A semiconductor memory device uses vertically stacked gate electrodes and conductive lines with varying counts at different levels to increase integration density.

Sequential masking and evaporation align organic functional layers with electrodes, resolving substrate deviation issues in roll-to-roll mass production.

Merging two OLED panels through a shared cathode layer eliminates redundant components, resolving the trade-off between dual-side functionality and device bulk.

Bonded glass cap wafers eliminate complex spacer structures while maintaining excellent optical quality in MEMS scanning mirrors.

Light-shielding layers with imaging holes integrate sensors under the screen to increase transmittance and improve the screen-to-body ratio.

Through via structures connect stacked electrode layers to peripheral logic, resolving manufacturing precision limits while managing device complexity.

A crosslinked polymeric dielectric layer with isocyanurate groups reduces charge trapping and hysteresis, improving electronic performance consistency.

A high-k dielectric pillar capacitor incorporates a blocking insulating pattern to prevent lower electrode oxidation and reduce current leakage.

Forming a recess between gate and drain electrodes increases storage capacitance, reducing driving power consumption for OLED displays.

Introducing narrower dummy photoresist patterns compensates for loading effects to ensure uniform etching depths across high-density device substrates.

Replacing heavy metal quantum dots with doped protein variants resolves environmental pollution risks while maintaining precise emission wavelength control.

A shock-absorbing layer buffers external impacts, reducing stress and structural deformation in foldable displays.

An asymmetric LED arrangement on a rectangular substrate resolves violet and green band artifacts by optimizing individual element distances from corners.

A heavy metal layer generates spin-polarized electrons to magnetize magnetic tunnel junction free layers via the Spin Hall effect.

Localized silicon and carbon doping in a III-V buffer layer improves surface flatness, maintaining crystallinity for high sensitivity light-receiving devices.

Soaking and spraying oxidizing solutions dope carbon nanotubes to reduce square resistance while maintaining flexibility.

A drain electrode with a larger area than the first electrode controls organic layer thickness in an OLED device.

Flexible substrates maintain uniform contact between columnar crystals and the pixel array, eliminating gaps from crystal length variations.

Merging active layer and gate patterning reduces mask count from nine to two, lowering OLED display production costs.

A dual-layer mask structure removes laser debris via water washing to suppress residual contamination during plasma dicing.

Graded barrier layers and chirped superlattices align valence bands in nBn detectors, reducing dark current across broader infrared wavelengths.

Oxidized insulation block in recessed channel access transistor gate mitigates gate-induced drain leakage and improves data retention.

A nanophotonic microlens array redirects incident light to focus on photosensitive cells within an optical sensor substrate.

Segmented gate electrode encloses photodiode region to prevent plasma damage during fabrication, enhancing photosensitivity and reliability.

A terminal connection structure uses conductive holes to link light emitting devices with arrayed terminals.

A stack type memory device uses a gate structure with side and top regions overlapping active layers to enhance integration density.

Graded epitaxial doping and isolation barriers prevent crosstalk in small-pixel back-illuminated imagers.

An image sensor replaces absorption filters with a color separation layer that routes wavelengths to specific cells, eliminating optical losses.

A multi-plenoptic system decomposes images into subfields using chief ray rotation and selective light modulation.

A micro/nano rugged layer and anti-reflection coating reduce total reflection at the semiconductor interface.

A monolithic III-nitride power device integrates a Schottky electrode to manage current switching within the semiconductor structure.

Novel organometallic compound integrates into OLED emission layers to enhance light output through stabilized molecular structures.

Stacking touch lines and source electrodes in different layers reduces opaque wiring regions on the array substrate.

Depositing a compressive polycrystalline silicon layer below 600°C counteracts tensile forces to keep wafer bow within acceptable limits.

A nitrogen-doped layer absorbs excess laser energy in overlap regions, preventing grain protrusion and ablation during semiconductor fabrication.

Epitaxial semiconductor layer forms pn junctions to eliminate edge breakdown, increasing opening area ratio and detection efficiency.

A stacked sub-pixel configuration distributes operational stress across multiple emissive layers to extend device longevity.

A light-transmissive primary cathode layer enables rear-side sensor placement on OLED panels for real-time luminance detection.

A resistive film traverses steps on a semiconductor substrate protrusion to elongate the electrical path.

A flexible OLED display uses identical cover and bottom films to prevent structural warpage while maintaining encapsulation integrity.

Deforming the reflective anode creates visible patterns without damaging small molecule OLED layers or compromising electrical conductivity.

Segmented ferroelectric gate insulation layers differentiate threshold voltages to prevent erroneous writing and erasing of adjacent memory cells.

Pre-formed phosphor tablets encapsulate LED dies with high thermal conductivity particles, reducing operating temperatures and preventing color shifting.

Multi-height standard cells route clock gate lines across vertical power rail levels, reducing occupation area and improving performance.

Local substrate doping prevents dopant diffusion to the channel layer, enhancing ground selection line reliability and ensuring consistent erasing speed.

Segmenting inorganic films with via holes reduces stress concentration during bending, preventing metal trace breakage and display defects.

A backplate manufacturing method applies a second passivation layer on metal electrodes before patterning the light shielding layer.

A display substrate integrates a crack stopper and detection line to block edge cracks and identify microcracks in the non-display region.

A light emitting device uses a thermally activated delayed fluorescence material and a crosslinked polymer layer to reduce driving voltage.

A photomask design featuring segmented light-shielding layers and translucent regions to control exposure.

A flat type semiconductor memory device incorporates a tantalum silicon nitride charge trap layer to enable efficient charge retention.

A pad part in non-display areas compensates for spacing gaps between magnetron sputtering targets to ensure uniform metal film thickness.

A polymer-based coating film composition dissolves in developer liquid to remove foreign substances from semiconductor substrates.

A fluorinated aromatic ring-based insulating polymer forms a gate layer that reduces moisture absorption in organic semiconductor elements.

Dual-polarity source pads inject electrons and holes into semiconductor strips to accelerate memory cell operations.

Selective epitaxial growth creates (100) and (110) oriented regions to resolve the trade-off between electron and hole mobility in NMOS and PMOS devices.

Dummy gates maintain uniform height during polishing, preventing fabrication failures from varying insulating layer thicknesses.

Separation portion protection films reduce stress concentrations at pixel boundaries, preventing cracks in the semiconductor substrate of an imaging element.

A segmented active layer structure combines organic semiconductors with high-mobility materials to boost charge transport speed.

Nitrogen gradient stabilizes conductive filaments, suppressing dissolution to improve data retention without increasing set voltage.

A monolithic HBT varactor uses a tuning layer to achieve wide-tuning range.

A shared contact hole connects multiple pixel drain electrodes to a single anode electrode, preventing turn-on defects caused by step changes in height.

A metal oxide and photoacid generator composition modifies the electron transport region to enhance electrical conductivity.

An ultrathin ferromagnetic layer within the magnetic tunnel junction improves spin filtering efficiency for higher signal margins.

Segmented main and auxiliary wirings reduce resistance while the auxiliary wiring blocks external moisture and oxygen penetration.

Variable hole transport layer thickness creates distinct microcavities to enhance specific wavelength ranges and reduce color deviation at large viewing angles.

Laser fusion creates crystal fused regions between pixels, eliminating trench grooves and preserving mechanical strength.

Comparator circuit activates power semiconductor via increased gate voltage to handle surge currents, resolving slow microcontroller response times.

Inductive coupling replaces thermocompression welding to eliminate delamination risks from mechanical stress and simplify production.

A light shielding layer with printed patterns conceals metal interconnection layers within a polarizing plate.

A thermosetting resin composition with white pigment delivers high light reflectance in optical semiconductor devices.

Increasing surface roughness on SOI wafer layers reduces stiction between components while maintaining secure bonding.

Metal plating fills contact holes to link bridge and touch electrodes, eliminating separate mask processes.

An inorganic insulating layer within a segmented dam structure prevents organic material overflow and reduces peeling off during manufacturing processes.

Conductive segments on adjacent bonding surfaces form a cross-wafer capacitor that reduces cross-capacitance and simplifies alignment.

Segmented annular and metal reflectors redirect light to reduce P-electrode absorption, resolving efficiency-reliability trade-offs.

A ferroelectric memory device uses a para-dielectric layer and charge trap site to generate negative capacitance effects.

A partition structure defines open regions for spacer formation, creating precise line and pad patterns through geometric transfer.

Segmenting the barrier layer exposes the mirror periphery, eliminating light absorption that reduces extraction efficiency in conventional LED chips.

A light scattering electrode combines electrical conduction and optical coupling in a single transparent matrix layer.

A flexible display device uses discontinuous inorganic insulating layers to act as stress relaxation sections between adjacent light emitting regions.

A fast/slow state machine latch generates select signals for a single toggle multiplexer circuit.

Segmented parallel regions in RRAM structures compensate for resistance drift to ensure stable data retention across switching cycles.

Flash memory cells on silicon-on-insulator substrates use buried oxide and shallow trench isolation to define independent cell columns.

Classifying via patterns to identify risk vias enables selective repositioning that corrects optical proximity effects without moving non-risk vias.

An air chamber formed by a deep trench and epitaxial layer minimizes electrical and optical cross-talk between pixels.

A mask plate pattern with narrower curve portions compensates for photolithography lateral light effects to maintain uniform fanout lead resistance.

Oriented anisotropic nanorods reduce charge trap sites to resolve hole leakage and delayed injection bottlenecks.

Metal semiconductor contact creates spatially varying depletion barriers in phase change memory selection elements.

A light source device uses a scattering unit to reduce light intensity before detection.