TFT Array Substrate Mask Reduction via Merged Patterning
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of OLED display panels is complex and costly due to the large number of required masks in traditional thin-film transistor (TFT) array substrate production.
Innovation Solution
A method for manufacturing a TFT array substrate that reduces the number of masks needed by forming a semiconductor pattern, gate, electrodes, and vias using a simplified sequence of steps, including semiconductor material deposition, gate insulating layer formation, metal film patterning, and interlayer dielectric layer processing, which results in a more efficient and cost-effective process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional mask processes are used to form active layer, gate, via, source, drain, electrode, opening, and spacer, then each component can be formed with precise control, but the number of masks increases to 9 and manufacturing complexity increases
Solution Approach 1:
The patent combines multiple mask processes into fewer mask steps by merging the formation of related components. Specifically, the first mask process simultaneously defines the active layer pattern and the first via pattern, while the second mask process simultaneously defines the gate pattern and the second via pattern. This merging approach reduces the total number of masks from 9 to 2 while maintaining precise control over component formation through carefully designed mask patterns that serve multiple functions.
Solution Approach 2:
Each mask in the invention serves multiple functions simultaneously. The first mask not only forms the active layer but also defines the first via openings, making it a universal patterning tool for two different components. Similarly, the second mask forms both the gate electrode pattern and the second via openings. This multi-functionality of masks reduces the overall number of masking operations required in the manufacturing process.
2Manufacturing precision
If traditional mask processes are used to form all components, then each component can be precisely positioned, but the product cost increases due to large number of masks
Solution Approach 1:
The patent merges multiple component formation operations into fewer mask processes. The first mask process combines active layer formation with first via formation, and the second mask process combines gate formation with second via formation. This merging reduces the number of masks from 9 to 2, directly lowering material costs and manufacturing expenses while maintaining precise component positioning through the designed mask patterns.
Solution Approach 2:
Each mask serves multiple purposes: the first mask creates both the active layer pattern and first via openings, while the second mask creates both the gate pattern and second via openings. This universal application of masks reduces the total number of masking operations, thereby reducing product cost while maintaining positioning precision through careful mask design that accounts for all required features.
3Productivity
If simplified mask process is used to reduce number of masks to 7, then manufacturing efficiency improves and cost decreases, but process complexity must be carefully managed
Solution Approach 1:
The patent achieves reduced process complexity by merging mask operations into exactly 2 mask processes (forming 7 components total). The first mask process combines active layer and first via formation, while the second mask process combines gate and second via formation. This strategic merging reduces the mask count from 9 to 2, improving manufacturing efficiency and reducing costs while managing process complexity through well-defined sequential steps for layer formation, doping, and electrode deposition.
Data Source
AI summary
A TFT array substrate and a method for manufacturing the same and an OLED display panel are provided. The method for manufacturing the TFT array substrate uses a mask to form an active pattern, a gate, a first electrode, a via and an opening in an interlayer dielectric layer and a gate insulating layer, a source, a drain, an opening in a planarization layer, and a spacer, respectively. The number of required masks is small and the processes are simple, which effectively improves the production efficiency and reduces the product cost.