Ferroelectric Memory Device with Charge Trap Site for Negative Capacitance
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Solution Overview
Problem
Conventional NAND flash memory devices face challenges with narrow refresh margins due to wide distribution of threshold voltage, leading to increased read time and power consumption, and ferroelectric field effect transistors suffer from data disturbance issues due to high pass voltages affecting unselected memory cells.
Innovation Solution
A non-volatile ferroelectric memory device with a para-dielectric layer and ferroelectric layer stack, incorporating a charge trap site for negative capacitance effects, and a control circuit that manages polarization inversion and depolarization to prevent interference between selected and unselected memory cells during programming, reading, and erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high pass voltage VPASS is applied to turn on unselected memory cells during read operation, then the selected memory cell can be read correctly, but the polarization direction of the ferroelectric layer in unselected memory cells changes causing data disturbance
Solution Approach 1:
The patent introduces a tunnel insulating layer as an intermediary between the control gate electrode and the ferroelectric layer. This tunnel insulating layer with specific thickness (5-20 nm) and dielectric constant (3-10) acts as a mediator that allows the high pass voltage to turn on the selected memory cell while preventing excessive electric field from directly affecting the ferroelectric layer, thus reducing polarization inversion in unselected cells
Solution Approach 2:
The patent changes the electrical parameters by applying different voltages to different parts of the memory cell. Specifically, it applies a first voltage to the control gate electrode and a second voltage (different from the first) to the semiconductor active layer, creating a voltage differential that enables precise control of the electric field distribution. This parameter change allows the system to achieve the desired turn-on effect while minimizing harmful effects on unselected cells
2Reliability
If conventional NAND flash memory device uses floating gate type or charge trap type memory cell transistors, then non-volatile storage is achieved, but the threshold voltage distribution is wide causing narrow refresh margin and increased read time
Solution Approach 1:
The patent replaces the conventional floating gate or charge trap type memory cell transistor structure with a ferroelectric field effect transistor. This substitution fundamentally changes the storage mechanism from charge-based to polarization-based, leveraging the non-volatile properties of ferroelectric materials. The ferroelectric layer's ability to maintain polarization states without continuous power enables narrow threshold voltage distribution and fast read operations while preserving non-volatile storage capability
3Power
If conventional NAND flash memory device operates at high voltage of about 20 V, then programming operation is achieved, but a special high voltage booster circuit is required increasing power consumption
Solution Approach 1:
The patent changes the operating voltage parameters by utilizing the unique electrical characteristics of ferroelectric materials. The ferroelectric field effect transistor can be programmed at lower voltages compared to conventional 20 V requirements. The tunnel insulating layer and ferroelectric layer combination enables efficient charge injection and trapping at reduced voltage levels, eliminating the need for complex high voltage booster circuits and reducing overall power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves the refresh margin by reducing threshold voltage dispersion and enhances operating speed while preventing data disturbance in ferroelectric field effect transistors, enabling efficient and fast memory operations with reduced power consumption.
Implementation Method 1
a dielectric stack having a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer
Implementation Method 2
the control circuit may invert a polarization in the ferroelectric layer of the unselected memory cell
Implementation Method 3
charges in the charge trap sites of the unselected memory cells may maintain a trap. Depolarization phenomenon of the ferroelectric layer may be induced by the electric charges trapped in the charge trap site and the inverted polarization of the ferroelectric layer
Data Source
AI summary
The present invention relates to a non-volatile ferroelectric memory device including a semiconductor active layer, a plurality of memory cells connected in series on the semiconductor active layer, and a control circuit for performing a read operation and a program operation on the selected memory cell among the plurality of memory cells, each of the memory cells comprising a para-dielectric layer on the semiconductor active layer; a dielectric stack including a ferroelectric layer stacked on the para-dielectric layer and a charge trap site for generating a negative capacitance effect of the ferroelectric layer by charges disposed and trapped at an interface between the ferroelectric layer and the para-dielectric layer; and a control gate electrode on the ferroelectric layer.