Fast/Slow State Machine Latch for Low Power Multiplexer Design
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Solution Overview
Problem
Conventional multiplexers suffer from high power consumption due to invalid data signal transitions, and existing low power multiplexer circuits are complex, hindering their adoption due to the extensive education required for their implementation.
Innovation Solution
A fast/slow state machine latch is introduced, which generates select signals for a single toggle, low power multiplexer circuit, allowing circuit designers to swap conventional logic with low power multiplexer circuits and fast/slow state machine latches, reducing power consumption while simplifying the design process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional multiplexer circuits are used, then ease of operation is maintained, but power consumption is excessive due to invalid data signal transitions
Solution Approach 1:
The patent introduces a state machine latch as an intermediary component between the data input and the multiplexer. This latch generates controlled select signals that mediate the data transmission, enabling the multiplexer to switch between valid and invalid data states. By using this intermediary, the circuit achieves low power consumption through controlled data transitions while maintaining ease of operation through standardized latch and multiplexer components.
2Use of energy by moving object
If low power multiplexer circuits are implemented, then power consumption is reduced, but device complexity increases requiring extensive education
Solution Approach 1:
The patent segments the low power multiplexer circuit into distinct, modular components: a state machine latch unit and a multiplexer unit. The state machine latch is further divided into sequential logic elements (D latch, XOR gate, inverter) that perform specific functions. This segmentation allows each component to be designed and analyzed independently, reducing overall circuit complexity while maintaining low power consumption benefits.
Solution Approach 2:
The patent changes the operational parameters of the multiplexer by introducing controlled timing states through the state machine latch. Instead of direct data switching, the circuit uses timed select signals with specific rise/fall times and transition sequences. This parameter change enables low power operation by ensuring data transitions occur only when necessary, while the standardized timing parameters keep the circuit design manageable.
3Loss of energy
If state machine latch with delayed and undelayed outputs is used, then invalid data transitions are minimized, but manufacturing precision requirements increase
Solution Approach 1:
The state machine latch implements periodic action through its clocked operation. The latch transitions between states at regular intervals defined by the clock signal, creating predictable periodic patterns in the select signals. This periodic behavior ensures that data transitions occur only at designated times when valid data is available, minimizing invalid transitions and reducing power consumption while maintaining achievable timing precision through standard clocking techniques.
Data Source
AI summary
A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.