Stack Type Semiconductor Memory Device With Side And Top Gate Regions
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Solution Overview
Problem
Existing memory devices face limitations in integration density and stability due to physical constraints and word line bouncing issues, particularly in resistive memory devices and phase-change memory devices, which hinder the development of next-generation memory devices with high capacity and low power consumption.
Innovation Solution
A stack type memory device is designed with a semiconductor substrate and multiple active layers, featuring a gate structure that includes both a side gate and a top gate region, along with a method of manufacturing that involves alternately stacking insulating and semiconductor layers, forming bit lines and resistive device layers, and patterning to create a three-dimensional structure that enhances integration density and prevents word line bouncing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a narrow linewidth word line is used to reduce area, then integration density is improved, but word line resistance increases causing word line bouncing and voltage instability
Solution Approach 1:
The patent transitions from planar word line routing to a three-dimensional stacked architecture where bit lines are arranged vertically in multiple layers. This dimensional change allows achieving high integration density without narrowing the word line linewidth, thereby maintaining low resistance and voltage stability while increasing storage capacity through vertical stacking of memory cells
Solution Approach 2:
The memory device is segmented into multiple stacked layers with bit lines distributed across different vertical levels. This segmentation allows parallel access to multiple memory layers through separate bit line segments, reducing the electrical load on individual word lines and preventing bouncing issues while maintaining compact area utilization
2Area of stationary object
If resistive memory devices are used to improve integration density, then capacity in limited area is improved, but physical limits of existing charge control devices are reached
Solution Approach 1:
The stacked memory architecture provides a universal platform that can accommodate different resistive memory materials (phase-change materials, oxide-based resistive memory) and cell configurations (1T1R, 1T2R) within the same structural framework. This multi-functional design achieves high integration density without requiring fundamentally different device structures for different memory technologies
Solution Approach 2:
The patent employs a nested structure where memory cells are stacked vertically with multiple active layers containing memory elements embedded within transistor structures. Each memory cell is nested within a three-dimensional configuration involving stacked electrodes, insulating layers, and conductive elements, achieving high density while managing structural complexity through hierarchical organization
Data Source
AI summary
A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.