Gate Structure Fabrication with Dummy Gate Height Uniformity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In semiconductor fabrication, the varying thicknesses of gate insulating layers can result in gate structures of different heights, leading to fabrication failures during processes like polishing, as existing methods struggle to ensure uniformity and successful replacement of dummy gates with metal gates across different transistor types.

Innovation Solution

A method is developed to fabricate gate structures with uniform heights by forming dummy gates with different insulating layers, polishing to expose all dummy gates, removing the thinner insulating layers, and forming new insulating layers of varying thicknesses to ensure uniform metal gate formation, including the use of oxide/nitride/oxide and oxide layers, and thermal oxidation processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If gate insulating layers of different thicknesses are formed for various transistor types, then the gate structures can accommodate different functional requirements, but the gate structures will have different heights causing fabrication failures

Engineering Contradiction:
Improvegate insulating layer thickness variationVSAvoidfabrication success rate
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

Dummy gates are formed in advance with a first gate insulating layer that has a uniform thickness across all regions. This preliminary structure allows subsequent selective removal of the dummy gates in specific regions while maintaining uniformity during intermediate fabrication processes like chemical mechanical polishing (CMP). The dummy gates serve as placeholders that enable uniform processing before the final gate structures are formed with their required different thicknesses.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct phases: first forming uniform dummy gates with a first gate insulating layer, then selectively removing dummy gates in certain regions, and finally forming the second gate insulating layer with varying thicknesses in different regions. This segmentation allows the process to maintain uniformity during critical steps while achieving the required variability in the final product.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If uniform gate structure height is maintained during fabrication, then fabrication processes can proceed without failure, but the final gate structures cannot have different insulating layer thicknesses for different functions

Engineering Contradiction:
Improvegate structure height uniformityVSAvoidgate insulating layer thickness variation
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

Dummy gates are formed in advance with a uniform first gate insulating layer thickness across all regions. This preliminary uniform structure enables subsequent selective removal of dummy gates in specific regions while maintaining uniformity during intermediate fabrication processes like chemical mechanical polishing (CMP). The dummy gates serve as placeholders that enable uniform processing before the final gate structures are formed with their required different thicknesses.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct phases: first forming uniform dummy gates with a first gate insulating layer, then selectively removing dummy gates in certain regions, and finally forming the second gate insulating layer with varying thicknesses in different regions. This segmentation allows the process to maintain uniformity during critical steps while achieving the required variability in the final product.

Inventive Principle:
Principle #1Segmentation

3Manufacturing precision

If dummy gates are removed selectively after forming inter-layer dielectric layer, then metal gates can be formed with correct thicknesses, but the process complexity increases

Engineering Contradiction:
Improvemetal gate thickness accuracyVSAvoidfabrication process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

Dummy gates are formed in advance with a uniform first gate insulating layer thickness across all regions. This preliminary uniform structure enables subsequent selective removal of dummy gates in specific regions while maintaining uniformity during intermediate fabrication processes like chemical mechanical polishing (CMP). The dummy gates serve as placeholders that enable uniform processing before the final gate structures are formed with their required different thicknesses.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct phases: first forming uniform dummy gates with a first gate insulating layer, then selectively removing dummy gates in certain regions, and finally forming the second gate insulating layer with varying thicknesses in different regions. This segmentation allows the process to maintain uniformity during critical steps while achieving the required variability in the final product.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach ensures that gate structures for various transistors are fabricated with reduced probability of failure, allowing for successful replacement of dummy gates with metal gates, thereby enhancing the reliability of transistor fabrication.

Implementation Method 1

The inter-layer dielectric layer is polished to expose all of the dummy gates

Methodology Applied
Scientific EffectChemical Mechanical Polishing (CMP):

Implementation Method 2

the second insulation layer is a thermal oxide layer by a thermal oxidation process on the substrate at the second region after the first gate insulation layer at the second region is removed

Methodology Applied
Scientific EffectThermal oxidation: Oxidation

Data Source

PatentUS11374109B2Method for fabricating gate structures
Publication Date: 2022.06.28 UNITED MICROELECTRONICS CORP
  • US11374109B2 patent drawing
  • US11374109B2 patent drawing
  • US11374109B2 patent drawing

AI summary

A method for fabricating gate structures includes providing a substrate, configured to have a first region and a second region. Dummy gate structures are formed on the substrate at the first and second regions, wherein each of the dummy gate structures has a first gate insulating layer on the substrate and a dummy gate on the first gate insulating layer. An inter-layer dielectric layer is formed over the dummy gate structures. The inter-layer dielectric layer is polished to expose all of the dummy gates. The dummy gates are removed. The first gate insulating layer at the second region is removed. A second gate insulating layer is formed on the substrate at the second region, wherein the first gate insulating layer is thicker than the second insulating layer. Metal gates are formed on the first and the second insulating layer.