Flat Type Semiconductor Memory Device TaSiN Charge Trap Layer
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Solution Overview
Problem
Conventional NAND flash memories face challenges with miniaturization, as the rocket type structure experiences interference between adjacent memory cell transistors, leading to malfunctions and difficulty in applying a sufficient electric field, which reduces charge accumulation and threshold variation control.
Innovation Solution
A semiconductor memory device with a flat type structure, incorporating a TaSiN layer as a charge trap layer between the polysilicon and TaN layers, and an AlO layer as an inter-poly dielectric, allowing for efficient charge retention and control electrode placement without interference, facilitating miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the rocket type structure is used to enhance control electrode power, then the controlling power is improved, but interference between adjacent memory cell transistors occurs and processing difficulty increases
Solution Approach 1:
The patent transitions from the conventional rocket type structure (vertical control electrode placement) to a flat type structure where the control electrode is positioned horizontally above the floating electrode. This dimensional change eliminates interference between adjacent memory cell transistors while maintaining effective control through the inter-poly dielectric layer and charge trap layer configuration.
2Ease of manufacture
If the flat type structure is used to eliminate interference, then ease of manufacture is improved, but controlling power of control electrode becomes weak
Solution Approach 1:
The patent employs a composite structure consisting of the inter-poly dielectric layer and the charge trap layer positioned between the control electrode and floating electrode. This composite configuration enhances the controlling power by creating a dipole effect that concentrates the electric field, thereby compensating for the reduced direct control electrode proximity while maintaining manufacturing simplicity.
Solution Approach 2:
The patent modifies the electrical parameters by introducing the charge trap layer with specific dielectric properties and creating a dipole configuration. This changes the electric field distribution and enhances the controlling power without requiring the control electrode to be in direct contact with the floating electrode, thus maintaining the ease of manufacture of the flat type structure.
3Power
If the floating electrode is thinned to enhance applied electric field, then controlling power is improved, but activation of polycrystalline silicon becomes difficult
Solution Approach 1:
The patent introduces the charge trap layer as an intermediary between the control electrode and the floating electrode. This intermediary layer enhances the applied electric field intensity through dipole formation without requiring thinning of the floating electrode, thereby preserving the polycrystalline silicon activation process and maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the write and erase operations by forming a dipole near the TaSiN and SiO layer interface, improving charge retention and reducing interaction between memory cell transistors, while simplifying manufacturing and maintaining high efficiency in the flat cell structure.
Implementation Method 1
forming a dipole near the TaSiN and SiO layer interface, improving charge retention
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a semiconductor member, a first insulating layer provided on the semiconductor member, a TaN layer provided on the first insulating layer and containing tantalum and nitrogen, a TaSiN layer provided on the TaN layer in contact with the TaN layer and containing tantalum, silicon, and nitrogen, a second insulating layer provided on the TaSiN layer in contact with the TaSiN layer and containing oxygen, and a control electrode provided on the second insulating layer.