Vertical Memory Devices With 3D Channels For Integration Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In VNAND flash memory devices, the channel hole needs to be large to expose the substrate surface adequately for proper connection, which complicates the manufacturing process and affects integration density.
Innovation Solution
A vertical memory device design featuring gate electrodes, a channel with vertical and horizontal portions, and an epitaxial layer that connects to the substrate, allowing for a trench structure without requiring a large channel hole, thus improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a large channel hole is used to expose the substrate surface, then the substrate can be adequately exposed for proper connection, but the manufacturing process becomes more complex and integration density decreases
Solution Approach 1:
The patent transitions from a conventional planar channel structure to a three-dimensional channel structure that extends vertically through stacked memory cells. The channel includes vertical portions extending through gate electrodes in the first direction and horizontal portions extending in the trench structure in the second direction, enabling substrate connection without requiring a large channel hole width
Solution Approach 2:
The channel is nested within a multi-layer structure comprising stacked gate electrodes, charge storage structures, and blocking patterns. The horizontal portion of the channel is embedded in the trench structure, while vertical portions pass through multiple gate electrode layers, creating a nested configuration that achieves substrate exposure through vertical stacking rather than horizontal expansion
2Manufacturing precision
If a large channel hole is used to expose the substrate surface, then proper substrate connection is achieved, but integration density decreases
Solution Approach 1:
The invention utilizes the vertical dimension by stacking multiple memory cell layers (first, second, and third memory cells) along the first direction. The channel connects to the substrate through vertical portions that extend through multiple gate electrodes, enabling adequate substrate exposure and connection while maintaining high integration density through vertical stacking rather than horizontal expansion
3Ease of operation
If a spacer is used to remove part of the ONO layer, then the upper surface of the substrate can be exposed, but the channel hole needs large width which complicates manufacturing
Solution Approach 1:
The patent employs a vertical channel structure where vertical portions extend through stacked gate electrodes in the first direction to expose the substrate upper surface. This vertical approach eliminates the need for large-width channel holes and complex spacer-based ONO layer removal processes, simplifying manufacturing while achieving adequate substrate exposure
Solution Approach 2:
The channel is segmented into distinct vertical portions and horizontal portions. The vertical portions extend through gate electrodes to expose the substrate, while horizontal portions extend in the trench structure to connect to the vertical portions, allowing independent optimization of each segment for simplified manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables a high degree of integration and efficient manufacturing by eliminating the need for a large channel hole, enhancing electrical characteristics and simplifying the manufacturing process.
Implementation Method 1
an epitaxial layer on a first portion of the substrate adjacent to each of opposite ends in the second direction of the gate electrodes, the epitaxial layer being connected to the horizontal portion of the channel
Data Source
AI summary
A vertical memory device includes a substrate having a trench structure, gate electrodes on the substrate, the gate electrodes being spaced apart from each other in a first direction substantially vertical to an upper surface of the substrate, a channel including a vertical portion extending through the gate electrodes in the first direction, and a horizontal portion extending in the trench structure in a second direction substantially parallel to the upper surface of the substrate, the horizontal portion being connected the vertical portion, and an epitaxial layer on a first portion of the substrate and connected to the horizontal portion of the channel, the first portion of the substrate being adjacent to ends of the gate electrode in the second direction.