Embedded Flash Memory on SOI Substrates with Isolation Regions
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Solution Overview
Problem
Current flash memory devices face challenges in manufacturing complexity, cost, and size reduction, particularly in embedded flash memory and SoC devices, due to the need for multiple lithography masks and the floating body effect when using silicon-on-insulator (SOI) substrates, which affects performance and reliability.
Innovation Solution
The formation of flash memory cells on SOI substrates with buried oxide for isolation, allowing each column of cells to be biased independently, reducing GIDL leakage and improving isolation, performance, and manufacturing efficiency by using shallow trench isolation and twin or triple well configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If flash memory cells are formed on SOI substrates to achieve high performance and lower power dissipation, then performance and power efficiency are improved, but the floating body effect occurs which deteriorates performance and reliability
Solution Approach 1:
The patent extracts the problematic floating body effect by introducing isolation regions that completely separate adjacent flash memory cells in the semiconductor layer. This extraction of the harmful floating body effect allows SOI substrates to be used for their power efficiency benefits without suffering from the reliability deterioration caused by floating body effects in conventional continuous semiconductor layer designs.
Solution Approach 2:
The patent segments the continuous semiconductor layer into isolated regions using isolation structures. By dividing the semiconductor layer into separate isolated regions, each flash memory cell is electrically isolated from its neighbors, preventing the floating body effect while maintaining the low power dissipation advantages of SOI substrates.
2Reliability
If conventional flash memory manufacturing methods are used, then flash memory functionality is achieved, but manufacturing complexity increases requiring more lithography masks and processing steps
Solution Approach 1:
The patent applies universality by using the same isolation regions for multiple purposes: they provide electrical isolation between flash memory cells, define cell boundaries, and enable independent biasing of cells. This multi-functionality reduces manufacturing complexity by eliminating the need for separate dedicated isolation structures that would require additional lithography masks and processing steps.
Solution Approach 2:
The patent merges the isolation function with the cell structure definition function into a single integrated structure. By combining these functions into unified isolation regions, the manufacturing process is simplified as fewer separate structures need to be formed, reducing the number of lithography masks and processing steps required.
3Area of moving object
If flash memory cell size is reduced to improve integration density, then device size is reduced, but manufacturing precision requirements increase making further size reduction difficult
Solution Approach 1:
The patent applies local quality by providing complete electrical isolation at each flash memory cell location through isolation regions. This localized isolation ensures that each cell maintains proper electrical characteristics independent of cell size, allowing further scaling to smaller dimensions without compromising manufacturing precision or cell performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and complexity, enhances performance, and avoids the floating body effect, enabling scalable and reliable flash memory devices with lower power dissipation and smaller size, while integrating flash memory on SOI substrates for SoC applications.
Implementation Method 1
a buried oxide layer disposed over the substrate... each isolation region extends completely through the layer of semiconductor material to the buried oxide layer
Implementation Method 2
each isolation region extends completely through the layer of semiconductor material... such that the body of each flash memory cell is electrically isolated from the bodies of each other flash memory cell
Data Source
AI summary
Flash memory device structures and methods of manufacture thereof are disclosed. The flash memory devices are manufactured on silicon-on-insulator (SOI) substrates. Shallow trench isolation (STI) regions and the buried oxide layer of the SOI substrate are used to isolate adjacent devices from one another. The methods of manufacture require fewer lithography masks and may be implemented in stand-alone flash memory devices, embedded flash memory devices, and system on a chip (SoC) flash memory devices.