Spin Hall Effect-Assisted STT-MRAM Parallel Write Scheme

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Solution Overview

Problem

Conventional STT-MRAM technologies face challenges with high write energy and insufficient switching speed, limiting their scalability and suitability for embedded system memory applications due to increased current density and power consumption as bit cells shrink.

Innovation Solution

The implementation of a Spin Hall effect (SHE)-assisted spin transfer torque (STT) operation in MRAM, which reduces write energy and increases switching speed by using a heavy metal layer to magnetize free layers of magnetic tunnel junctions through a parallel write scheme, enabling nanosecond switching with moderate current and external magnetic field control.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If conventional STT-MRAM is used to store data in smaller bit cells, then memory density increases, but write energy and power consumption increase

Engineering Contradiction:
Improvememory densityVSAvoidwrite energy
Core Design Contradiction:
Quantity of substanceVSUse of energy by moving object

Solution Approach 1:

The patent introduces a heavy metal layer as an intermediary component between the bit line and the magnetic tunnel junction. This heavy metal layer generates spin-polarized electrons that assist in switching the magnetic state, thereby reducing the write energy required for smaller bit cells while maintaining or increasing memory density

Inventive Principle:
Principle #24Intermediary (Mediator)

2Quantity of substance

If conventional STT-MRAM is used to store data in smaller bit cells, then memory density increases, but switching speed decreases

Engineering Contradiction:
Improvememory densityVSAvoidswitching speed
Core Design Contradiction:
Quantity of substanceVSSpeed

Solution Approach 1:

The heavy metal layer acts as a mediator that provides spin-polarized electrons to assist in the magnetic switching process. This intermediary mechanism enables faster switching speeds even as bit cell size decreases and memory density increases, overcoming the speed limitations of conventional STT-MRAM

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces write energy and increases the density and throughput of STT-MRAM, making it suitable for embedded memory applications by enabling faster switching times and lower write energies, while maintaining high-density bit cell arrays.

Implementation Method 1

uses a Spin Hall effect (SHE) to assist in modifying a magnetic layer of a magnetic tunnel junction during a spin transfer torque (STT) operation

Methodology Applied
Scientific EffectSpin Hall Effect: Hall Effect

Implementation Method 2

During the write operation, the spin-polarized electrons exert a torque on the free layer, which can switch the polarity of the free layer

Methodology Applied
Scientific EffectSpin Transfer Torque:

Implementation Method 3

A change in the polarity of the free layer will change the resistance of the MTJ storage element. For example, when the polarities are aligned, a low resistance state exists. When the polarities are not aligned, then a high resistance state exists

Methodology Applied
Scientific EffectMagnetoresistance: Magnetoresistance

Data Source

PatentUS10460785B1Parallel write scheme utilizing spin hall effect-assisted spin transfer torque random access memory
Publication Date: 2019.10.29 QUALCOMM INC
  • US10460785B1 patent drawing
  • US10460785B1 patent drawing
  • US10460785B1 patent drawing

AI summary

A magnetoresistive random access memory (MRAM) and associated apparatus and methods are described. The MRAM generally includes a heavy metal layer coupled to a source line, and a plurality of bit cells coupled to a word line, a plurality of bit lines, and the heavy metal layer, such that the heavy metal layer is a continuous layer coupling the bit cells to the source line, wherein each of the bit cells comprises a magnetic tunnel junction (MTJ) and a transistor, a gate of the transistor being coupled to the word line, and at least one of a source or a drain of the transistor being coupled to the MTJ or at least one of the bit lines.