Semiconductor Via Retargeting for Risk Mitigation
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Solution Overview
Problem
Current semiconductor device design methods face challenges in achieving high reliability and performance due to issues like optical proximity effects in photolithography, leading to process errors and integration density limitations, which affect the accuracy and efficiency of metal pattern formation and via placement.
Innovation Solution
A method involving a retargeting process to correct shapes and positions of metal patterns, followed by classifying and repositioning risk vias based on process risks, such as proximity effects, to minimize process risks and ensure accurate via placement without moving non-risk vias, thereby improving the design rule check and fabrication accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a retargeting process is performed to correct shapes and positions of metal patterns, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The via patterns are segmented into two categories: risk vias that require position adjustment and non-risk vias that maintain original positions. This segmentation allows selective correction of only those vias susceptible to optical proximity effects, improving manufacturing precision while limiting the complexity increase to only the necessary portions of the design.
Solution Approach 2:
Different treatment is applied to different via patterns based on their local characteristics. Risk vias located near metal patterns (within a threshold distance) receive position correction through the retargeting process, while non-risk vias maintain their original positions. This local quality approach ensures manufacturing precision is improved where needed without unnecessarily complicating the entire design process.
2Reliability
If risk vias are repositioned to reduce process risks, then reliability is improved, but manufacturing precision requirements increase
Solution Approach 1:
The retargeting process performs preliminary position adjustment of risk vias before the actual fabrication process. By pre-correcting the positions of vias that are susceptible to optical proximity effects, the patent ensures that the final via placement achieves the required reliability without imposing stricter precision requirements on the manufacturing process itself.
3Manufacturing precision
If all via patterns are repositioned to ensure accuracy, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
Instead of repositioning all via patterns, the patent applies the retargeting process only to risk vias that meet specific criteria (distance to metal patterns within a threshold). This partial action approach maintains via placement accuracy for critical regions while avoiding unnecessary processing of non-risk vias, thereby preserving layout design efficiency and overall productivity.
Data Source
AI summary
A method of designing a layout of a semiconductor device includes preparing a layout for a semiconductor integrated circuit, the preparing of the layout including providing lower and upper metal patterns and via patterns, which are vertically interposed between the lower and upper metal patterns, performing a retargeting process on the lower and upper metal patterns, classifying the via patterns to extract at least one risk via from the via patterns and changing a position of the risk via. During the changing of the position of the risk via, all of the via patterns, other than the risk via, are unchanged in position thereof. Related systems and computer program products are disclosed.