Ferroelectric Memory Cell Segmentation for Erase Error Prevention
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Solution Overview
Problem
Nonvolatile memory cells with ferroelectric field effect transistors face issues with erroneous writing/erasing due to the design, where intended memory cells are accidentally erased during the erasing process.
Innovation Solution
A semiconductor memory design incorporating ferroelectric transistors with specific wiring connections and ferroelectric materials in the gate insulation layers, allowing for precise control over data writing and erasing operations by utilizing the polarization state of the ferroelectric layers to differentiate threshold values and manage data states effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ferroelectric field effect transistors are used to replace transistors in the latch portion of SRAM, then nonvolatile data storage is achieved, but erroneous writing/erasing occurs in memory cells that are not intended to be erased
Solution Approach 1:
The patent divides the gate insulation layer into multiple segments with different ferroelectric materials or structures. Specifically, the gate insulation layer includes a first region with a first ferroelectric material and a second region with a second ferroelectric material, allowing different threshold voltages to be applied to different memory cells. This segmentation enables selective erasing of only the intended memory cell while preventing erroneous erasure of adjacent cells, as each region responds to different voltage levels.
Solution Approach 2:
The patent applies different ferroelectric materials or structures to different regions of the gate insulation layer, creating local variations in electrical properties. The first region has different ferroelectric characteristics than the second region, allowing each region to be controlled independently with different threshold voltages. This local quality differentiation enables precise control over which memory cell is erased, eliminating the harmful effect of unintended erasure.
2Device complexity
If a single gate insulation layer structure is used for simplicity, then device complexity is reduced, but selective control over writing and erasing operations becomes difficult
Solution Approach 1:
The gate insulation layer is segmented into multiple regions with different ferroelectric materials, creating a structure that is more complex than a single-layer design but enables precise selective control. The segmentation allows different voltage thresholds to be applied to adjacent memory cells, making selective writing and erasing operations possible while maintaining a relatively simple overall transistor architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design prevents erroneous writing/erasing, ensuring accurate data storage and retrieval by leveraging the unique properties of ferroelectric materials to maintain data integrity and reduce errors in memory operations.
Implementation Method 1
A gate insulation layer of a third transistor includes a first ferroelectric material. A gate insulation layer of a fourth transistor includes a second ferroelectric material.
Data Source
AI summary
A semiconductor memory includes a first and a second transistor each with one of source/drain connected to a first wiring. The other of the source/drain for each of first and second transistor is connected to the gate of the other transistor. A third and a fourth transistor each have gates connected to a second wiring, one of source/drain of each connected to a third or fifth wiring, the other of the source/drain connected to the other of the source/drain of the first or second transistor. For the third transistor, a gate insulation layer includes a first ferroelectric material. For the fourth transistor, and a gate insulation layer includes a second ferroelectric material.