Semiconductor Device with Local Doping for Erasing
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Solution Overview
Problem
In vertically stacked semiconductor devices, the diffusion of N-type dopants from the substrate to the channel layer affects the functionality of ground selection line devices, leading to impaired performance.
Innovation Solution
A semiconductor device design with a substrate having a lower N-type doping concentration, featuring two stacks with different doping concentrations for conductive connectors, where the erasing voltage is applied to a second conductive connector rather than the substrate, and distinct voltages are applied to each stack to manage channel layer voltages during erasing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the substrate has a high N-type doping concentration to ensure good electrical contact and low resistance, then the electrical conductivity is improved, but the N-type dopant diffuses upward through the channel layer affecting the ground selection line device functionality
Solution Approach 1:
The substrate is designed with non-uniform doping concentration, where the lower doping concentration region is positioned adjacent to the channel layer to minimize dopant diffusion, while other regions maintain higher doping concentrations to ensure proper electrical contact and device functionality. This local variation in doping quality resolves the contradiction between electrical conductivity and dopant diffusion.
2Productivity
If the erasing voltage is applied to the substrate to perform block erasing operation, then the erasing function is achieved, but the N-type dopant diffusion to the channel layer is enhanced, affecting ground selection line device
Solution Approach 1:
An intermediate conductive layer is introduced between the substrate and the channel layer. This intermediate layer serves as a mediator that allows the erasing voltage to be applied effectively for block erasing operations while preventing direct dopant diffusion from the substrate to the channel layer. The intermediate layer decouples the erasing function from the dopant diffusion pathway.
3Object-affected harmful factors
If the substrate doping concentration is reduced to prevent dopant diffusion, then the dopant diffusion is reduced, but the electrical contact and conductivity may be compromised
Solution Approach 1:
The substrate employs spatially varying doping concentrations, with lower doping levels in regions adjacent to the channel layer to prevent dopant diffusion, and higher doping levels in contact regions to maintain electrical conductivity. This local differentiation allows simultaneous optimization of both dopant diffusion prevention and electrical contact quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces dopant diffusion to the channel layer, enhances the utilization of ground selection line devices, and ensures consistent erasing speed across memory cells by maintaining different internal voltages in the channel layers.
Implementation Method 1
the diffusion of the N-type dopant of the substrate of the semiconductor device to the channel layer which affects the ground select line device (GSL device) can be alleviated
Data Source
AI summary
A semiconductor device includes a substrate including a doped region of a first doping concentration that extends downward from an upper surface of the substrate; a first stack on the upper surface, including first insulating layers and first conductive layers alternatively stacked, a first channel layer, a first memory layer and a first conductive connector configured to receive a first voltage, the first conductive connector on the first channel layer, having a second doping concentration; a second stack on the first stack including second insulating layers and second conductive layers alternatively stacked, a second channel layer, a second memory layer, the second conductive layer configured to receive the second voltage; a second conductive connector on the second channel layer, configured to receive an erasing voltage, the first conductive connector electrically connected to the first and second channel layers; the first doping concentration smaller than the second doping concentration.