RCAT Gate Insulation Block for Leakage Reduction
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Solution Overview
Problem
Conventional recessed channel access transistor (RCAT) devices suffer from gate-induced drain leakage (GIDL) due to a sharp upper corner of the poly gate and a thinner gate oxide layer, which affects the refresh and data retention characteristics of DRAM devices.
Innovation Solution
A method is developed to fabricate an RCAT device by forming a semiconductor substrate with a recess, depositing a gate dielectric layer and gate material layer, creating a dielectric cap layer, etching to form a gate pattern, forming a liner layer and spacer, and then oxidizing the exposed gate material layer to form an insulation block in an undercut recess, thereby reducing the concentrated electric field.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional RCAT device uses a sharp upper corner poly gate structure, then the gate channel length is physically increased to suppress short channel effect, but a concentrated electric field occurs at the cell side leading to gate-induced drain leakage
Solution Approach 1:
The patent applies curvature by replacing the sharp upper corner of the poly gate with a rounded or curved corner structure. This geometric modification eliminates the concentrated electric field at the sharp corner while maintaining the recessed gate structure's ability to suppress short channel effects. The curved corner distributes the electric field more uniformly, preventing GIDL formation.
Solution Approach 2:
The patent modifies only the local geometry of the gate corner region while maintaining the overall recessed gate structure. By applying a different geometric quality (curved vs. sharp) specifically at the corner region where electric field concentration occurs, the solution addresses the GIDL problem locally without compromising the global short channel effect suppression provided by the recessed gate structure.
2Reliability
If the gate oxide layer is made thinner near the poly gate corner, then the gate control is improved, but the electric field concentration increases causing leakage
Solution Approach 1:
By curving the gate corner geometry, the patent eliminates the sharp interface that causes electric field concentration. This allows the gate oxide layer to maintain its thin dimension for good gate control while the curved corner distributes the electric field, preventing the leakage that would otherwise occur at sharp corners.
3Reliability
If the lateral area of the gate electrode is increased to suppress short channel effect, then the gate channel length increases, but the device integration density decreases
Solution Approach 1:
The patent transitions from a planar gate structure to a recessed gate structure that utilizes the vertical dimension. By etching the gate into the substrate to form a recess, the gate channel length is extended in the vertical direction rather than requiring a larger lateral area. This maintains integration density while achieving short channel effect suppression through increased effective gate length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate-induced drain leakage, improving the refresh and data retention characteristics of DRAM devices by mitigating the short channel effect and enhancing the integration density of RCAT transistors.
Implementation Method 1
The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein
Data Source
AI summary
A method for fabricating a recessed channel access transistor device is provided. A semiconductor substrate having thereon a recess is provided. A gate dielectric layer is formed in the recess. A gate material layer is then deposited into the recess. A dielectric cap layer is formed on the gate material layer. The dielectric cap layer and the gate material layer are etched to form a gate pattern. A liner layer is then formed on the gate pattern. A spacer is formed on the liner layer on each sidewall of the gate pattern. The liner layer not masked by the spacer is etched to form an undercut recess that exposes a portion of the gate material layer. The spacer is then removed. The exposed portion of the gate material layer in the undercut recess is oxidized to form an insulation block therein.