High-k Dielectric Pillar Capacitor with Blocking Insulator
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Solution Overview
Problem
In high-integration semiconductor devices, capacitors face challenges in achieving sufficient capacitance within a limited area due to the inverse proportionality of capacitance to equivalent oxide thickness and the need for high dielectric constants, while existing technologies struggle with current leakage and oxidation issues.
Innovation Solution
A method of manufacturing a semiconductor device with a metal-insulator-metal (MIM) capacitor that involves forming a high-k dielectric pattern with a pillar shape, a lower electrode, and a blocking insulating pattern of lower dielectric constant, where the blocking insulating pattern is thicker than the high-k dielectric pattern, and an upper electrode is formed to cover both, with specific heat treatments and material selections to prevent oxidation and enhance capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the equivalent oxide thickness of the dielectric layer is reduced to increase capacitance, then capacitance increases, but current leakage increases
Solution Approach 1:
The patent uses a composite dielectric structure consisting of a high-k dielectric layer (first dielectric layer) and a low-k dielectric layer (second dielectric layer). The high-k layer provides high capacitance, while the low-k layer on top provides low leakage, combining the advantages of both materials to resolve the contradiction between high capacitance and low leakage.
2Quantity of substance
If high-temperature heat treatment is performed to form high-k dielectric layer, then dielectric constant increases, but lower electrode oxidizes
Solution Approach 1:
The lower electrode is formed before the high-k dielectric layer is deposited and before the high-temperature heat treatment. This preliminary formation allows the lower electrode to be protected from oxidation during subsequent high-temperature processes, as the high-k dielectric layer acts as a protective barrier.
Solution Approach 2:
The high-temperature heat treatment is performed in an oxygen atmosphere to form the high-k dielectric layer, but the lower electrode is protected from oxidation because it is covered by the high-k dielectric layer which prevents direct contact with oxygen.
3Quantity of substance
If the surface area of electrode is increased by increasing height or using HSG to increase capacitance, then capacitance increases, but device complexity increases
Solution Approach 1:
The patent applies different dielectric properties to different locations: the first dielectric layer (high-k) is applied to the sidewalls of the lower electrode to maximize capacitance in the vertical direction, while the second dielectric layer (low-k) is applied to the upper surface to minimize leakage. This local differentiation achieves high capacitance without requiring complex electrode geometries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases capacitance and reduces current leakage, improving the electrical characteristics of the MIM capacitor by preventing oxidation of the lower electrode during high-temperature processes and utilizing materials with high work functions for oxidation resistance.
Implementation Method 1
performing a first heat treatment to the high-k dielectric layer in an oxygen atmosphere at a temperature of about 500° C. to 1000° C.
Implementation Method 2
forming an upper dielectric layer having a same crystalline structure as the high-k dielectric pattern by using the high-k dielectric pattern as a seed
Data Source
AI summary
A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern.