Semiconductor Memory Devices With Variable Conductive Line Density
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Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing integration density due to the high cost of equipment needed to form fine patterns, making it difficult to enhance their manufacturing efficiency and reliability.
Innovation Solution
The semiconductor memory device employs a stack structure with vertically stacked gate electrodes, a vertical channel, and conductive lines arranged in multiple layers, where the number and pitch of conductive lines vary at different levels, allowing for increased integration density without the constraints of available space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of metal interconnections is increased to improve integration density, then the integration density improves, but the device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar interconnection to three-dimensional stacked interconnection. Multiple conductive lines are arranged in different vertical levels (first level, second level, third level) to connect to gate electrodes, enabling increased integration density by utilizing the vertical dimension rather than only horizontal plane.
Solution Approach 2:
The interconnection structure is segmented into multiple conductive lines at different levels. Each conductive line is selectively connected to specific gate electrodes through connection contacts, allowing independent control and reducing the complexity of managing all interconnections as a single unit.
2Ease of manufacture
If the number of conductive lines at each level is made equal, then the manufacturing process is simplified, but the space utilization is inefficient
Solution Approach 1:
The patent applies different numbers of conductive lines at different vertical levels based on local requirements. The first conductive lines at the first level, second conductive lines at the second level, and third conductive lines at the third level have different quantities optimized for their respective positions, improving space utilization while maintaining manufacturing feasibility through selective connection.
Data Source
AI summary
A semiconductor memory device includes a stack structure including gate electrodes vertically stacked on a substrate and a vertical channel part penetrating the gate electrodes, a bit line connected to the vertical channel part, and a plurality of conductive lines connected to the gate electrodes on the stack structure. The conductive lines form a plurality of stacked layers and include first conductive lines and second conductive lines. The number of the first conductive lines disposed at a first level from the substrate is different from the number of the second conductive lines disposed at a second level from the substrate. The first level is different from the second level.