3D Semiconductor Layout With Offset Contacts for Reliable Scaling
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Solution Overview
Problem
As semiconductor devices are scaled down, their operating characteristics deteriorate due to increased device density, leading to challenges in achieving improved performance and reliability.
Innovation Solution
A three-dimensional semiconductor device is designed with stacked active regions, including lower and upper source/drain patterns connected through channel patterns, and gate electrodes, along with active contacts that are offset and insulated to enhance device density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device density is increased by scaling down MOSFET sizes, then more transistors can be integrated, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar MOSFET arrangement to three-dimensional vertical stacking, where multiple active regions are stacked above each other in the vertical direction. This allows increased device density without further scaling down individual transistor dimensions, thereby maintaining operating characteristics while achieving higher integration density.
Solution Approach 2:
The patent divides the semiconductor device into multiple discrete active regions (first active region, second active region, third active region) stacked vertically, each with its own source/drain patterns and channel patterns. This segmentation allows independent optimization of each layer while achieving high overall density.
2Quantity of substance
If multiple active regions are stacked vertically, then device density increases, but process complexity increases
Solution Approach 1:
The patent merges multiple processing steps into unified operations. For example, a single etching process forms contact holes that penetrate through multiple interlayer dielectric layers to reach source/drain patterns in different active regions simultaneously. Multiple source/drain patterns are formed using the same epitaxial growth and doping processes, reducing process complexity despite the three-dimensional structure.
3Reliability
If active contacts are offset and insulated from upper source/drain patterns, then electrical properties are maintained, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces interlayer dielectric layers as intermediary elements between active contacts and source/drain patterns. These dielectric layers provide electrical insulation and physical spacing, allowing active contacts to be offset from upper source/drain patterns while maintaining proper electrical connections to lower source/drain patterns. The intermediary layers buffer alignment tolerances and simplify manufacturing precision requirements.
Data Source
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AI summary
Disclosed are three-dimensional semiconductor devices and their fabrication methods. The 3D semiconductor device includes a first active region (AR1) on a substrate and including a lower channel pattern (CH1) and a lower source/drain pattern (SD1) connected to the lower channel pattern (CH1), a second active region (AR2) above the first active region (AR1) and including an upper channel pattern (CH2) and an upper source/drain pattern (SD2) connected to the upper channel pattern (CH2), at least one gate electrode (GE1, GE2) on the lower and upper channel patterns (CH1, CH2), a first active contact (AC1) electrically connected to the lower source/drain pattern (SD1), and a second active contact (AC2) electrically connected to the upper source/drain pattern (SD2). A first central line (C1) of the lower source/drain pattern (SD1) and a second central line (C2) of the upper source/drain pattern (SD2) in a vertical direction are offset from each other in a first direction perpendicular to the vertical direction. The first active contact (AC1) and the second active contact (AC2) are spaced apart from each other in the first direction.