3D Single-Crystal Semiconductor Stacking With Dense Oxide Bonding
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Solution Overview
Problem
Current semiconductor fabrication methods face challenges with high mask-set costs and low flexibility, limiting the production of commercially viable logic families with diverse products, and existing 3D IC technologies are constrained by large Through-Silicon Vias (TSVs) that restrict the number of connections that can be made.
Innovation Solution
The development of a 3D IC device fabrication method using a re-programmable antifuse in conjunction with Through Silicon Via (TSV) technology, allowing for the construction of configurable logic devices with multiple layers of antifuses for power distribution and interconnection, and employing layer transfer techniques to create thin, high-density connections, reducing the size of TSVs to less than one micron for increased connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional fabrication methods are used, then manufacturing process is well-established, but mask-set costs are high and flexibility is low
Solution Approach 1:
The patent implements re-programmable antifuse technology that allows the semiconductor device to be dynamically reconfigured after fabrication. The antifuse structures can be programmed in different states to create different logic functions, enabling the same physical device to adapt to different computational requirements without requiring new mask sets or fabrication processes.
2Productivity
If existing 3D IC technologies are used, then vertical integration is achieved, but Through-Silicon Vias are large and restrict connection density
Solution Approach 1:
The patent transitions from traditional through-silicon via connections to surface-level interconnect structures that route signals along the surface of the semiconductor substrate. This dimensional change from vertical penetration to surface routing allows for much higher connection density without requiring large TSV structures, enabling more connections per unit area in the 3D IC architecture.
3Adaptability or versatility
If multiple mask sets are used for diverse product production, then product variety is increased, but manufacturing costs are increased
Solution Approach 1:
The patent creates a universal semiconductor device platform using re-programmable antifuse technology that can be configured to implement different logic families and product specifications. A single fabrication process produces devices that can be programmed afterward to serve multiple functions, eliminating the need for separate mask sets for different products and thereby reducing manufacturing costs while maintaining product variety.
Data Source
AI summary
A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where each of the first transistors includes a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; a first oxide layer disposed over the second metal layer; a second oxide layer disposed over the first oxide layer; and a second level including at least one array of memory cells and second transistors, where each of the memory cells includes at least one of the second transistors, where the second level overlays the first level, where at least one of the second transistors includes at least two independent gates, where the second level is directly bonded to the first level, and where the bonded includes direct oxide-to-oxide bonds.