3D Semiconductor Pillar Layout for High-Density SGT Fabrication
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Solution Overview
Problem
Current methods for manufacturing three-dimensional semiconductor devices, particularly Surrounding Gate Transistors (SGTs), face challenges in achieving high-density pillar-shaped semiconductor devices with precise integration and high performance.
Innovation Solution
A method involving multiple material layer formations, etchings, and polishings to create a three-dimensionally-shaped semiconductor layer with precise control over the dimensions and positioning of semiconductor pillars, allowing for the formation of high-density SGTs with optimized gate insulating and conductor layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MOS transistor structures are used, then manufacturing process is simple, but device density and integration level are limited
Solution Approach 1:
The patent transitions from two-dimensional planar MOS transistor structures to three-dimensional pillar-shaped SGT structures. The channel extends vertically from the substrate surface, creating a pillar structure that utilizes the third dimension (depth) to increase device density. This dimensional change allows multiple channels to be packed into a smaller planar footprint while maintaining manufacturing feasibility through adapted fabrication processes.
2Area of stationary object
If pillar-shaped SGT structures are formed, then chip size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The manufacturing process is divided into multiple sequential steps including forming sacrificial layers, creating patterns, depositing materials, and selective removal. Each step breaks down the complex task of pillar formation into manageable segments with controlled precision requirements. The use of band-like material layers and systematic etching processes allows for precise pillar formation while maintaining overall process feasibility.
3Manufacturing precision
If multiple material layers are formed and processed, then pillar structure precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent combines multiple material layers (first, second, third, fourth, fifth material layers) and processing steps into an integrated manufacturing sequence. The band-like material layers are formed, processed, and removed in a coordinated manner to simultaneously define multiple pillars with precise dimensions. This merging of operations achieves high precision while managing process complexity through systematic integration.
Data Source
AI summary
A second band-like mask material layer having a first band-like mask material layer of a same planar shape on its top is formed on a mask material layer on a semiconductor layer. Then, fourth band-like mask material layers having third band-like mask material layers of same planar shape on their top are formed on both side surfaces of the first and second band-like mask material layers. Sixth band-like mask material layers having fifth band-like mask material layers of same planar shape on their top are formed on the outside thereof. Then, an orthogonal band-like mask material layer is formed on the first band-like mask material layer, in a direction orthogonal to a direction in which the first band-like mask material layer extends. Semiconductor pillars are formed on overlapping areas of this orthogonal band-like mask material layer and the second and sixth band-like mask material layers by etching the semiconductor layer. Then, a pillar-shaped semiconductor device is formed with these semiconductor pillars being channels.