Nanoinformatics TRIZ Cases

Using a (110) substrate, rectangular boron-doped silicon buffer layers resist etchant leakage and protect source/drain junctions during gate replacement.

Ion implantation raises STI etch resistance before recessing, reducing liner mismatch, dishing, and channel damage in GAA transistor fabrication.

Plasma-conditioned upper source/drain surfaces enable selective epitaxial growth on the lower feature, forming lower-resistance C-FET contacts.

Insulating fins separate semiconductor fins to stop epitaxial source/drain coalescing, preserving nano-FET integrity and SRAM gate layout.

A protection layer shields the isolation feature during replacement gate etching, reducing shorts and parasitic capacitance in GAA transistors.

A widened spacer opening formed by plasma oxidation enables gate deposition around nanowires while preserving precision at smaller nano-FET feature sizes.

Selective fluorine diffusion into gate dielectrics cuts charge buildup and leakage paths, improving GAA and FinFET reliability.

Cap layers between sacrificial and channel layers block dopant diffusion during channel release, preserving etch selectivity and drive current.

Selective dipole annealing changes gate dielectric composition so p-type GAA transistors can achieve different threshold voltages in one flow.

Crystallizing gate dielectric layers lowers etch rate and improves selectivity during work function layer patterning, reducing dielectric loss.

Reordering PFET and NFET work-function metal steps avoids NFET oxidation, improving speed and threshold uniformity in memory devices.

Conformal metal deposition thickens corner silicide in source/drain contacts, enlarging landing area and lowering transistor contact resistance.

A funnel-shaped gate trench and dielectric spacers laterally confine the metal cap to cut parasitic capacitance and leakage current.

Dielectric helmets define gate cut locations in 3D fin FET fabrication, reducing overlay-driven errors and widening the metal gate etch window.

Embedded carbon nanotubes create parallel source-drain conduction paths, enabling sub-1 nm transistor scaling with higher drive current.

An insulating layer beneath the bottom gate cuts leakage current and parasitic PN junctions in GAA fin structures, improving ION/IOFF ratio.

Fluorine-based dry etching forms square openings and thicker inner spacers in GAA fin structures, reducing epitaxial defects from wet etch limits.

Alternating chlorine- and fluorine-based etches create a necking profile that fully clears GAA source/drain regions and avoids residue.

Varying nanosheet count and width by functional block balances power use, speed, and manufacturability in one semiconductor chip.

Selective etching and dopant diffusion tune hGAA threshold voltage without channel defects, while improving electrostatic control.

Using (110)-oriented nanostructures and separated epitaxial layers, this case improves nano-FET current flow and source/drain growth.

A cap layer extending between the gate metal and spacers cuts parasitic capacitance while supporting stronger GAA gate control.

Selective etch-resistant and capping layers protect dielectric regions while preserving contact area to lower interconnect resistance and leakage.

An amorphous Ge layer and annealing create a strain-relaxed single-crystal SiGe channel that cuts defects and dislocations while improving mobility.

Oxygen plasma converts part of a metal gate layer into metal oxide, enabling reliable GAA nanostructures with precise pitch control and lower parasitic capacitance.

Different crystal directions for fin programming and nanosheet reading transistors extend breakdown time while preserving anti-fuse programming.

A hybrid GAA nanosheet and FinFET layout improves gate control, lowers OFF-state current, and mitigates short-channel effects in scaled CMOS.

Sequential metal gate formation with selective etching improves GAA gate height control and fabrication yield despite patterning complexity.

Selective multi-step etching shapes GAA nanostructures and removes sacrificial layers without damaging semiconductor integrity.

A conductive sidewall layer redirects plasma into high-aspect-ratio trenches, enabling bottom-up fill with fewer seams and voids.

Floating dummy gate and MD layers at the well border block 1.8 V input from reaching the well, preventing current leaks in scaled semiconductor structures.

An Al-C work-function layer between the high-k dielectric and p-type gate metal lowers pFET threshold voltage by dipole formation.

A bottom dielectric isolation region replaces punch-through implantation to cut leakage and capacitance in scaled nanosheet transistors.

Sacrificial plugs isolate top nanoribbon channels during workfunction metal etching, enabling dual metal gates with tighter stack spacing.

Selective dielectric treatment forms inner spacers in GAA nanowire transistors to cut gate-source/drain capacitance and improve gate control.

Self-aligned trenches and metal-filled holes create backside wiring for stacked FETs, cutting misalignment and parasitic capacitance.

Pre-etching high-k and isolation layers forms slanted STI sidewalls that cut leakage current and improve semiconductor reliability.

A shared isolation trench and vertical interconnect layout boosts stacked FET density, cuts resistance, and avoids extra lithography steps.

Hydrogen and nitrogen plasma effluents condition low-k silicon-containing layers for selective self-limited etching with less residue and substrate damage.

A wider-base, narrower-top fin profile cuts line edge roughness and channel resistance to improve 3D transistor switching and reliability.

An aluminum-carbon interlayer in the pFET gate stack forms dipoles with high-k dielectric to raise work function and lower threshold voltage.

Nitridation of the CESL and oxide curing of the ILD improve source/drain adhesion while limiting oxidation and contamination diffusion.

Selective p-dipole annealing diffuses elements into the gate dielectric, enabling p-type GAA transistors with distinct threshold voltages on one IC.

An oxygen-doped barrier layer between source/drain epitaxial layers blocks impurity diffusion and helps FinFETs limit short channel effects.

A gate shield insulating pattern and layered gate stack suppress short channel effects while improving current control and reliability.

Segmented source/drain silicide in stacked GAA channels improves gate control, lowers OFF-state current, and eases contact formation.

Concave inner spacers in nanostructure transistors reduce fabrication voids and defects, improving yield and transistor performance.