P-Type GAA Gate Dielectric Tuning for Multi-Threshold Voltage
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Solution Overview
Problem
Existing GAA transistors do not adequately address the need for transistors with different threshold voltages for various functions, such as power saving, standard, and high-performance modes, leading to inefficiencies in IC design and manufacturing.
Innovation Solution
A method involving the formation of a gate dielectric layer over a workpiece with a p dipole layer and a hard mask layer, followed by selective removal and thermal annealing to create transistors with varying threshold voltages by altering the composition of the gate dielectric layer in specific regions, resulting in p-type GAA devices with distinct electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing GAA transistor processes are used, then manufacturing simplicity is maintained, but the ability to provide transistors with different threshold voltages for various functions is insufficient
Solution Approach 1:
The patent applies local quality by forming different gate dielectric layer compositions in different device regions. Specifically, a first gate dielectric layer composition is formed in a first device region while a second gate dielectric layer composition is formed in a second device region, enabling different threshold voltages for transistors in different regions without requiring completely separate fabrication processes
Solution Approach 2:
The patent segments the gate dielectric layer formation process into region-specific steps. The method involves selectively forming gate dielectric layers with different compositions in different device regions through separate deposition or annealing steps, allowing independent control of threshold voltages for different transistor functions (e.g., power saving mode vs. high-performance mode)
2Adaptability or versatility
If gate dielectric layer composition is altered to change threshold voltage, then transistor functionality for different modes is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by forming a uniform gate dielectric layer across all device regions before performing selective regional treatments. The method first deposits a gate dielectric layer that substantially fills gaps between nanostructures in all regions, then subsequently performs selective removal or annealing in specific regions to create the desired composition variations. This preliminary uniform formation simplifies the overall process control
Solution Approach 2:
The patent changes physical or chemical parameters of the gate dielectric layer to achieve different threshold voltages. Specifically, it alters the dielectric constant or composition of the gate dielectric layer in different regions through selective removal of portions or selective annealing processes, thereby tuning the threshold voltage of transistors in different device regions without requiring precise control of multiple deposition parameters
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the fabrication of p-type GAA transistors with different threshold voltages, enhancing the functionality and efficiency of integrated circuits by accommodating diverse performance requirements.
Implementation Method 1
annealing the workpiece to drive elements in the first p dipole layer and the second p dipole layer into corresponding portions of the gate dielectric layer thereunder
Data Source
AI summary
Semiconductor structures and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece comprising a first channel member directly over a first region of a substrate and a second channel member directly over the first channel member, the first channel member being vertically spaced apart from the second channel member, conformally forming a dielectric layer over the workpiece, conformally depositing a dipole material layer over the dielectric layer, after the depositing of the dipole material layer, performing a thermal treatment process to the workpiece, after the performing of the thermal treatment process, selectively removing the dipole material layer, and forming a gate electrode layer over the dielectric layer.