Nanosheet Transistor Bottom Dielectric Isolation for Leakage Control
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Solution Overview
Problem
Nanosheet transistor devices face increased leakage and capacitance issues due to diminished effectiveness of punch-through layers with gate length scaling, creating a tradeoff between reduced leakage and increased device capacitance.
Innovation Solution
Implementing a bottom dielectric isolation region formed through a deposition process that integrates with gate spacers, reducing device capacitance and leakage current while allowing for gate length scaling, and incorporating a thin semiconductor layer to enhance source/drain epitaxial crystallinity and act as an additional channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If punch-through implantation is used to reduce leakage, then leakage is reduced, but device capacitance increases
Solution Approach 1:
The patent extracts the punch-through layer from the device structure and replaces it with a bottom dielectric isolation region. This removal eliminates the source of increased capacitance while maintaining the leakage reduction function through the dielectric isolation, thereby resolving the contradiction between leakage reduction and capacitance control
Solution Approach 2:
The patent changes the material parameter from doped semiconductor (punch-through layer) to dielectric material (isolation region). This parameter change fundamentally alters the electrical characteristics, providing leakage blocking through dielectric properties rather than through doped semiconductor properties, thus avoiding the capacitance penalty associated with punch-through implantation
2Length of moving object
If gate length is scaled down to narrow length, then device density is improved, but leakage increases due to diminished punch-through layer effectiveness
Solution Approach 1:
The patent transitions from a lateral punch-through layer approach to a vertical bottom dielectric isolation approach. By moving the isolation function to the vertical dimension beneath the nanosheet stack, the solution remains effective even as gate length scales down laterally, thereby resolving the contradiction between gate length scaling and leakage control
3Object-generated harmful factors
If increased doping via punch-through implantation is applied, then leakage is reduced, but device capacitance increases
Solution Approach 1:
The patent replaces the permanent doped punch-through layer with a dielectric isolation region that can be formed and removed more easily. The bottom sacrificial layer serves as a temporary structure during fabrication that is subsequently removed, leaving the dielectric isolation in place. This approach avoids the need for increased doping and its associated capacitance penalties
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces leakage current and capacitance without compromising gate length scaling, enhancing device performance and energy efficiency by integrating a bottom dielectric isolation region and a thin semiconductor layer.
Implementation Method 1
forming a gate spacer and an isolation region by concurrently forming an insulating material on the nanosheet stack and in the opening, respectively
Implementation Method 2
epitaxially growing a semiconductor layer from the sacrificial layer
Data Source
AI summary
Methods of forming transistor devices are provided. A method of forming a transistor device includes providing a nanosheet stack that includes a plurality of nanosheets on a substrate. A sacrificial layer is between the nanosheet stack and the substrate. The method includes removing the sacrificial layer to form an opening between the nanosheet stack and the substrate. The method includes forming a gate spacer and an isolation region by forming an insulating material on the nanosheet stack and in the opening, respectively. Related transistor devices are also provided.