Gate Spacer Funnel Trench Layout for Lower Leakage Current
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Solution Overview
Problem
Existing multi-gate semiconductor devices, such as FinFETs and GAA transistors, face challenges in reducing parasitic capacitance and leakage current, which affect performance and efficiency.
Innovation Solution
A method involving the formation of a funnel-shaped trench in the gate stack, followed by the deposition of dielectric spacers and a metal cap, laterally confined by these spacers, to reduce the distance between the metal cap and neighboring source/drain contacts, thereby minimizing parasitic capacitance and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices (FinFETs, GAA transistors) are used to improve gate control, then gate-channel coupling is improved and off-state current is reduced, but parasitic capacitance increases due to the complex three-dimensional structure
Solution Approach 1:
The gate structure is segmented into multiple gates wrapping around the channel from different directions (e.g., top and sidewalls in FinFETs, or completely surrounding in GAA transistors). This segmentation provides superior gate control and electrostatic control over the channel while managing parasitic capacitance through spatial distribution
Solution Approach 2:
The gate structure transitions from a planar two-dimensional configuration to a three-dimensional multi-gate configuration. The gate wraps around the channel in multiple dimensions (top surface and sidewalls), enhancing gate control and reducing off-state current while the vertical stacking in GAA transistors further optimizes the control-to-capacitance ratio
2Reliability
If multi-gate devices are used to reduce off-state current, then leakage current is reduced, but device complexity increases due to the multi-gate structure
Solution Approach 1:
The device is segmented into multiple gate structures positioned at different locations around the channel. Each gate segment independently controls a portion of the channel, achieving superior off-state current reduction while the modular segmented approach allows for systematic fabrication processes
Solution Approach 2:
The gate structure is nested around the channel in a multi-layer configuration. In FinFETs, the gate wraps around the top and sidewalls; in GAA transistors, multiple gates are nested vertically around the channel, providing comprehensive control while maintaining a compact integrated structure
3Object-generated harmful factors
If the metal cap is positioned closer to source/drain contacts to reduce parasitic capacitance, then parasitic capacitance and leakage current are reduced, but manufacturing precision requirements increase
Solution Approach 1:
Dielectric spacers are formed in advance around the gate structure before depositing the metal cap. These pre-formed spacers establish precise lateral boundaries that automatically position the metal cap at the optimal distance from source/drain contacts, eliminating the need for complex post-alignment operations and reducing manufacturing precision requirements
Solution Approach 2:
Dielectric spacers are introduced as intermediary structures between the gate/metal cap and the source/drain contacts. These spacers act as physical barriers and positioning references, laterally confining the metal cap and maintaining precise spacing relationships without requiring direct alignment between the metal cap and source/drain contacts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed method results in reduced parasitic capacitance and leakage current, leading to improved performance and efficiency of semiconductor devices.
Implementation Method 1
performing an etching process to recess the gate spacers and the gate structure
Implementation Method 2
depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench
Data Source
AI summary
Semiconductor devices and methods are provided. An exemplary method according to the present disclosure includes providing a workpiece having a channel region, a gate structure over the channel region, gate spacers extending along sidewalls of the gate structure, and an etch stop layer extending along sidewalls of the gate spacers. The method also includes performing an etching process to recess the gate spacers and the gate structure, thereby forming a funnel-shaped trench, depositing a dielectric layer over the workpiece to partially fill the funnel-shaped trench, etching back the dielectric layer to form dielectric spacers on the recessed gate spacers, forming a metal cap on the gate structure without forming the metal cap on the recessed gate spacers, and forming a dielectric cap on the metal cap.