GAA Inner Spacer Structure for Lower Gate-to-Source Capacitance
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Solution Overview
Problem
The integration of gate-all-around (GAA) devices in semiconductor manufacturing is challenging due to complexities in fabricating features around nanowires, particularly in reducing parasitic capacitance between the gate stack and source/drain features.
Innovation Solution
A method is introduced to form an inner spacer layer between the gate stack and source/drain features using a dielectric material, which involves treating the dielectric material to create an etching selectivity, allowing controlled removal of treated portions to form the inner spacer layer, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional fabrication methods are used for GAA devices, then manufacturing process compatibility is maintained, but parasitic capacitance between gate stack and source/drain features increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming the core structure, depositing dielectric material, selectively removing portions, and forming the inner spacer layer. This segmentation allows each step to be optimized independently, reducing parasitic capacitance while maintaining compatibility with conventional CMOS processes.
Solution Approach 2:
An inner spacer layer is introduced as an intermediary structure between the gate stack and source/drain features. This intermediate layer physically separates the gate and source/drain regions, reducing parasitic capacitance coupling while maintaining structural integrity and compatibility with existing fabrication processes.
2Reliability
If inner spacer layer is formed to reduce parasitic capacitance, then gate control is improved, but manufacturing process complexity increases
Solution Approach 1:
The dielectric material is deposited and selectively treated before final patterning steps. This preliminary action prepares the structure for subsequent inner spacer formation, enabling precise control over gate-channel coupling while using standard fabrication techniques to minimize manufacturing complexity.
Solution Approach 2:
The dielectric material undergoes parameter changes through selective treatment (e.g., etching, deposition, or material transformation) that creates regions with different properties. This allows the inner spacer layer to be formed with precise thickness and positioning, improving gate control while using controllable, scalable processes.
3Manufacturing precision
If dielectric material is treated to create etching selectivity, then inner spacer layer precision is improved, but process steps increase
Solution Approach 1:
The dielectric material is treated locally rather than uniformly, creating etching selectivity only in specific regions where the inner spacer layer needs to be formed. This local treatment approach achieves high precision in spacer layer positioning and thickness while minimizing additional process steps by treating only the necessary areas.
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a plurality of nanowire structures over a fin structure, and a gate stack wrapping around the plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.