Anti-Fuse Memory Layout With Split Crystal Directions

Solution Overview

Problem

Existing anti-fuse memory devices with nanosheet transistors have compromised reading transistor performance due to identical or similar crystal lattice directions, leading to undesirable shorter breakdown times and reduced reliability.

Innovation Solution

Configuring the programming transistor as a fin-based transistor and the reading transistor as a nanosheet transistor with different crystal lattice directions, specifically <110> for the programming transistor and <100> for the reading transistor, to maintain decent programming performance while improving reading transistor reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the programming transistor and reading transistor are configured with identical or similar crystal lattice directions, then the manufacturing process is simplified, but the reading transistor reliability deteriorates due to shorter breakdown times

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidreading transistor reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies local quality by assigning different crystal lattice directions to different transistor types within the same memory device. Specifically, the programming transistor is configured with a first crystal lattice direction while the reading transistor is configured with a second crystal lattice direction different from the first. This localized differentiation allows each transistor type to be optimized for its specific function, with the reading transistor's crystal structure optimized for reliability and breakdown time characteristics.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the crystal lattice direction parameter between different transistor types to resolve the contradiction. By modifying this fundamental material parameter, the patent achieves both manufacturing feasibility and improved reading transistor reliability. The different crystal lattice directions result in different breakdown characteristics, with the reading transistor exhibiting longer breakdown times and enhanced reliability.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If the reading transistor uses a crystal lattice direction optimized for reliability, then the breakdown time extends and reliability improves, but the programming performance may be compromised

Engineering Contradiction:

Improvereading transistor reliabilityVSAvoidprogramming performance

Core Design Contradiction:

ReliabilityVSEase of operation

Solution Approach 1:

The patent applies local quality by assigning different crystal lattice directions to different transistor types within the same memory device. Specifically, the programming transistor is configured with a first crystal lattice direction while the reading transistor is configured with a second crystal lattice direction different from the first. This localized differentiation allows each transistor type to be optimized for its specific function, with the reading transistor's crystal structure optimized for reliability and breakdown time characteristics.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent changes the crystal lattice direction parameter between different transistor types to resolve the contradiction. By modifying this fundamental material parameter, the patent achieves both manufacturing feasibility and improved reading transistor reliability. The different crystal lattice directions result in different breakdown characteristics, with the reading transistor exhibiting longer breakdown times and enhanced reliability.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12464811B2Memory devices and methods of manufacturing thereof

Publication Date: 2025.11.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.