Semiconductor Isolation Structure With Slanted STI Sidewalls
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Solution Overview
Problem
The shadowing effect of high-k dielectric layers and plasma charging at isolation layers during the formation of insulating structure openings in semiconductor devices leads to portions of fin structures and substrate remaining adjacent to STI regions, increasing leakage current and decreasing device reliability and performance.
Innovation Solution
The method involves reducing the height of high-k dielectric and isolation layers by etching and forming slanted sidewalls at the top portions of STI regions, allowing for the removal of more fin structures and substrate, thereby reducing leakage current and improving device reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-k dielectric layers and isolation layers are maintained at their original height during insulating structure opening formation, then the structural integrity and electrical isolation are preserved, but shadowing effects and plasma charging occur that increase leakage current and reduce device reliability
Solution Approach 1:
The patent applies preliminary action by performing etching of the high-k dielectric layer and isolation layer before forming the insulating structure openings. This pre-etching creates slanted sidewalls and removes material in advance, preventing the shadowing effect and plasma charging that would otherwise occur during subsequent processing steps, thereby reducing leakage current and improving device reliability
Solution Approach 2:
The patent introduces a dimensional change by creating slanted sidewalls instead of vertical walls during the etching process. This angular geometry allows the etch process to reach and remove fin structures and substrate material that would be shadowed by vertical sidewalls, effectively addressing the leakage current issue from a geometric perspective
2Object-generated harmful factors
If the height of high-k dielectric and isolation layers is reduced by etching to remove more fin structures and substrate, then leakage current is reduced, but the structural support and electrical isolation provided by these layers are compromised
Solution Approach 1:
The patent applies local quality by selectively etching the high-k dielectric layer and isolation layer only in specific regions where insulating structure openings are to be formed. The etching creates slanted sidewalls localized to these opening regions, removing fin structures and substrate material precisely where needed to reduce leakage current, while leaving the rest of the layers intact to maintain overall structural support and electrical isolation
Solution Approach 2:
By performing the etching operation before forming the insulating structures, the patent removes problematic fin structures and substrate material in advance. This preliminary removal prevents leakage current paths from forming, while the insulating structures are subsequently formed in the created openings to provide the necessary structural support and electrical isolation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces leakage current by an order of 10^2 to 10^4, enhancing device reliability and performance by minimizing the shadowing and plasma charging effects.
Implementation Method 1
reducing the height of high-k dielectric and isolation layers by etching
Implementation Method 2
plasma charging at isolation layers during the formation of insulating structure openings
Data Source
AI summary
The present disclosure describes a structure that provides insulation in a semiconductor device and a method for forming the structure. The structure includes a first isolation structure including a first isolation layer disposed on a substrate, a second isolation layer disposed on the first isolation layer, and a first high-k dielectric layer having a first height and disposed on the second isolation layer. The structure further includes a second isolation structure including a third isolation layer disposed on the substrate, a fourth isolation layer disposed on the third isolation layer, and a second high-k dielectric layer having a second height and disposed on the fourth isolation layer, where the second height is less than the first height. The structure further includes a gate structure disposed on the first isolation structure, and an insulating structure disposed adjacent to the gate structure and on the second isolation structure.