GAA Nanostructure Profiling Through Selective Sacrificial Layer Etching
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Solution Overview
Problem
As semiconductor devices continue to reduce minimum feature sizes for increased integration density, challenges arise in the fabrication of Gate All Around (GAA) transistors, particularly in shaping the nanostructures and removing sacrificial layers without damaging the semiconductor nanostructures.
Innovation Solution
A method is developed for forming GAA transistors by creating a multilayer stack with semiconductor nanostructures and sacrificial layers, followed by etching processes to shape the nanostructures and remove the dummy gate stack, including the use of specific etching gases and materials to maintain the integrity of the nanostructures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to remove sacrificial layers and shape nanostructures, then manufacturing simplicity is maintained, but the semiconductor nanostructures are damaged or degraded
Solution Approach 1:
The etching process is divided into multiple sequential steps with different etching chemistries: first etching to remove sacrificial layers, second etching to shape nanostructures, and third etching to remove dummy gate stacks. Each step uses optimized conditions specific to the target material, preventing damage to remaining structures.
Solution Approach 2:
A dummy gate stack is introduced as an intermediary structure that protects the semiconductor nanostructures during the etching process. The dummy gate stack serves as a sacrificial element that can be selectively removed later, allowing precise control over nanostructure shaping without direct exposure to harsh etching conditions.
2Productivity
If feature sizes are reduced to increase integration density, then more components are integrated into a given area, but additional fabrication problems arise that damage nanostructures
Solution Approach 1:
Different regions of the structure receive different treatments through selective etching. The etching process is localized to specific areas (sacrificial layers, dummy gate stacks) while preserving the semiconductor nanostructures. This allows precise control over local profile formation without affecting overall nanostructure integrity.
Solution Approach 2:
The dummy gate stack is formed in advance before the final nanostructure shaping steps. This preliminary structure serves as a template and protective layer that guides subsequent etching operations, ensuring that when the dummy gate is removed, the nanostructures have already been properly shaped and protected.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively shapes the nanostructures and removes sacrificial layers, enhancing the performance of GAA transistors by maintaining the integrity and profile of the semiconductor nanostructures, thereby improving device performance.
Implementation Method 1
An etching process may then be performed to remove the germanium intermix layers on the surfaces of the semiconductor nanostructures. The profile of the nanostructures is also shaped through the etching process.
Data Source
AI summary
A method includes forming a multilayer stack, which includes a plurality of semiconductor layers and a plurality of sacrificial layers located alternatingly. The method further includes forming a dummy gate stack on the multilayer stack, etching the multilayer stack to form a trench, epitaxially growing a semiconductor region in the trench to form a source/drain region, and removing the plurality of sacrificial layers from the multilayer stack. After the sacrificial layers are removed, an etching process is performed. After the etching process, a gate stack is formed around the plurality of semiconductor layers.