Isolation Structures With Vertical Interconnects for Stacked FETs
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Solution Overview
Problem
The complexity of semiconductor manufacturing processes increases with the scaling down of semiconductor devices, such as MOSFETs, finFETs, and GAA FETs, necessitating a solution to enhance device density without compromising electrical isolation and requiring fewer process steps.
Innovation Solution
The implementation of stacked FETs with vertical interconnect structures and isolation structures formed in a cut-metal-gate process, which reduces device area occupation and resistance by integrating vertical interconnects within isolation structures, using a single photolithographic and etch process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional isolation structures are used between FETs, then electrical isolation is maintained, but device density is reduced and process complexity increases
Solution Approach 1:
The patent combines the isolation structure and vertical interconnect structure into a single integrated formation process. The isolation trench is formed, then filled with dielectric material and conductive material in sequence, creating both the isolation barrier and the vertical interconnect simultaneously. This merging of functions reduces the number of separate manufacturing steps while maintaining both electrical isolation and interconnect functionality.
Solution Approach 2:
The isolation structure serves multiple functions: it provides electrical isolation between adjacent FETs, acts as a support structure for vertical interconnects, and enables compact device layout. By making the isolation structure multi-functional, the patent eliminates the need for separate structures for each function, thereby increasing device density and reducing process complexity.
2Reliability
If vertical interconnect structures are formed adjacent to isolation structures, then electrical isolation is maintained, but device area is increased and resistance is higher
Solution Approach 1:
The patent nests the vertical interconnect structure within the isolation structure. The conductive material is deposited into the isolation trench, creating a vertical interconnect that is physically contained within the isolation barrier. This nesting arrangement allows the vertical interconnect to share the same spatial footprint as the isolation structure, significantly reducing the overall device area while maintaining electrical isolation between adjacent FETs.
3Manufacturing precision
If multiple process steps are used for isolation and interconnect formation, then manufacturing precision is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent merges the isolation formation and vertical interconnect formation into a single integrated process sequence. The isolation trench is formed first, then dielectric material is deposited to fill portions of the trench, followed by conductive material deposition to create the vertical interconnect. This combined approach maintains manufacturing precision through controlled material deposition while reducing the total number of process steps, thereby lowering manufacturing cost and complexity.
Data Source
AI summary
A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.