Multigate Source/Drain Silicide Layout for Stronger GAA Gate Control
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Solution Overview
Problem
Multigate devices, particularly gate-all-around (GAA) devices, face performance degradation due to challenges associated with the addition of multiple stacked channel layers during IC manufacturing, which complicates the manufacturing process and affects device performance.
Innovation Solution
A method for fabricating multigate devices that includes forming multiple voids in the source/drain region by etching semiconductor layers to create facets with a (111) crystallographic orientation, followed by growing epitaxial source/drain features with controlled voids to enhance gate control and reduce short-channel effects, and forming a silicide feature in the source/drain contact opening to improve contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple stacked channel layers are added to GAA devices to improve performance, then gate control and short-channel effect mitigation are enhanced, but manufacturing complexity increases and device performance degrades
Solution Approach 1:
The source/drain region is segmented into multiple discrete silicide features rather than a continuous structure. Each silicide feature corresponds to a specific channel layer interface, enabling independent optimization of electrical contact for each stacked channel while simplifying the overall manufacturing process by breaking down the complex multi-layer contact formation into manageable discrete steps.
2Reliability
If multiple stacked channel layers are added to GAA devices, then short-channel effects are reduced, but OFF-state current increases due to manufacturing challenges
Solution Approach 1:
The silicide features are strategically positioned at specific locations where source/drain contacts are needed for each individual channel layer, rather than forming a continuous blanket contact. This localised contact approach allows precise control of electrical properties at each channel interface, reducing parasitic effects and minimizing OFF-state current leakage while preserving the beneficial short-channel effect mitigation of stacked channels.
3Ease of manufacture
If conventional source/drain contact formation is used in GAA devices, then manufacturing is simplified, but contact formation quality deteriorates
Solution Approach 1:
The silicide features are formed preliminarily during the source/drain region fabrication process, before final contact formation steps. This preliminary silicide deposition and patterning creates pre-defined contact regions that guide subsequent processing steps, ensuring high precision contact alignment and quality while maintaining compatibility with conventional manufacturing workflows through integrated process design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the performance of multigate devices by improving gate control, reducing OFF-state current, and mitigating short-channel effects, while maintaining compatibility with conventional IC manufacturing processes.
Implementation Method 1
forming multiple voids in the source/drain region by etching semiconductor layers to create facets with a (111) crystallographic orientation
Implementation Method 2
growing epitaxial source/drain features with controlled voids to enhance gate control and reduce short-channel effects
Implementation Method 3
forming a silicide feature in the source/drain contact opening to improve contact formation
Data Source
AI summary
Source/drain silicide that improves performance and methods for fabricating such are disclosed herein. An exemplary device includes a first channel layer disposed over a substrate, a second channel layer disposed over the first channel layer, and a gate stack that surrounds the first channel layer and the second channel layer. A source/drain feature disposed adjacent the first channel layer, second channel layer, and gate stack. The source/drain feature is disposed over first facets of the first channel layer and second facets of the second channel layer. The first facets and the second facets have a (111) crystallographic orientation. An inner spacer disposed between the gate stack and the source/drain feature and between the first channel layer and the second channel layer. A silicide feature is disposed over the source/drain feature where the silicide feature extends into the source/drain feature towards the substrate to a depth of the first channel layer.