Insulating Fin Layout to Prevent Nano-FET Source/Drain Coalescing
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in maintaining the integrity and functionality of transistor structures, particularly in nano-FETs, due to issues like coalescing of epitaxial source/drain regions during growth.
Innovation Solution
The formation of insulating fins, also known as hybrid or dielectric fins, is introduced between semiconductor fins to prevent coalescing of epitaxial source/drain regions, using materials with high etching selectivity and controlled growth processes to create distinct gate structures for transistors, especially in static random-access memory (SRAM) cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial source/drain regions are grown in semiconductor fins, then device functionality is achieved, but coalescing of adjacent regions occurs causing loss of device integrity
Solution Approach 1:
The patent introduces insulating fins that physically divide and segment the semiconductor fins, creating isolated growth regions. This segmentation prevents the coalescing of epitaxial source/drain regions by inserting insulating barriers between adjacent semiconductor fins, thereby maintaining device integrity while allowing epitaxial growth to proceed.
Solution Approach 2:
The insulating fins act as intermediary structures positioned between adjacent semiconductor fins. These intermediary insulating features prevent direct contact and coalescing of epitaxial regions while still allowing the device to function, serving as a mediating element that resolves the conflict between achieving device functionality and preventing region coalescing.
2Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated, but maintaining structural integrity becomes more difficult
Solution Approach 1:
By introducing insulating fins as periodic segmentation elements, the patent enables higher integration density through reduced minimum feature sizes while maintaining structural integrity. The segmented structure with insulating barriers prevents coalescing even at smaller dimensions, allowing continued scaling and increased component integration.
3Reliability
If insulating fins are introduced to prevent coalescing, then device integrity is maintained, but process complexity increases
Solution Approach 1:
The insulating fins are formed in advance before the epitaxial growth step, serving as pre-positioned barriers. This preliminary action ensures that when epitaxial source/drain regions are subsequently grown, the insulating fins are already in place to prevent coalescing, simplifying the overall process by preventing problems before they occur rather than requiring complex corrective steps.
Data Source
AI summary
In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.