Dielectric Helmet Gate Isolation for Accurate Metal Gate Cuts
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Solution Overview
Problem
Existing semiconductor fabrication methods, such as cut-poly-gate (CPO) and cut-metal-gate (CMG) processes, face issues like insufficient metal track placement and overlay errors during photolithography, leading to inaccurate cutting results, especially when processing gates with different critical dimensions.
Innovation Solution
A method involving the formation of isolation features using a series of photolithography and etching processes to create three-dimensional fins separated by dielectric materials, followed by the deposition of cladding and isolation structures, and the formation of dielectric helmets to enhance gate isolation, allowing for better control of the metal gate etch process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cut-metal-gate (CMG) process is used to provide isolation features between metal gate structures, then isolation is achieved, but overlay errors during photolithography lead to inaccurate cutting results
Solution Approach 1:
The patent forms dielectric helmets over the metal gate structures before performing the metal gate etch process. These helmets serve as pre-established isolation features that define the cut locations, allowing the etch process to proceed without relying on photolithography overlay alignment. The helmets are formed in advance and provide a robust template for the subsequent etching step, eliminating overlay errors.
Solution Approach 2:
The dielectric helmets act as an intermediary structure between the photolithography step and the metal gate etch process. Instead of directly using photolithography patterns to define cut locations (which suffer from overlay errors), the helmets serve as a mediating element that transfers the isolation geometry in a more accurate and reliable manner through the etch process.
2Productivity
If gates with different critical dimensions are processed simultaneously, then productivity is maintained, but inaccuracies occur in cutting results
Solution Approach 1:
The etch process parameters are optimized to accommodate gates with different critical dimensions. By adjusting etch selectivity, power, and other parameters, the process can accurately define cut locations for various gate sizes simultaneously without requiring separate processing steps, thus maintaining productivity while improving cutting accuracy.
Data Source
AI summary
A method includes forming first and second semiconductor fins protruding from a substrate. Each of the first and second semiconductor fins includes a stack of alternating channel layers and non-channel layers. The method also includes forming a dielectric helmet between and protruding from the first and the second semiconductor fins, forming a dummy gate stack over the dielectric helmet, patterning the dummy gate stack to expose a portion of the dielectric helmet, removing the exposed portion of the dielectric helmet, and forming a metal gate structure, such that a remaining portion of the dielectric helmet separates the metal gate structure between the first and the second semiconductor fins. The method also includes forming a contact feature over a portion of the metal gate structure. A sidewall of the contact feature is between one of the semiconductor fins and the remaining portion of the dielectric helmet.