Multi-Gate Nanostructure Transistors With Cap Layers for Channel Release
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Solution Overview
Problem
The formation of multi-bridge-channel (MBC) transistors is challenged by dopant diffusion from sacrificial layers into channel layers, leading to defects such as buckling and reduced drive current, due to the lack of effective etch selectivity and control during the removal of sacrificial layers.
Innovation Solution
The implementation of at least one cap layer, comprising a first cap layer in contact with sacrificial layers and a second cap layer in contact with channel layers, to control dopant diffusion and etch selectivity, using germanium-tin (GeSn) and undoped germanium (Ge) for the cap layers to protect the channel layers during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sacrificial layers are removed to release channel layers, then channel members are freed for gate wrapping, but dopant diffusion occurs causing buckling and reduced drive current
Solution Approach 1:
A cap layer is introduced as an intermediary between the sacrificial layer and the channel layer. This cap layer serves as a protective barrier that prevents dopant diffusion from the sacrificial layer into the channel layer during the etching process, while still allowing the sacrificial layer to be removed to release the channel members.
Solution Approach 2:
The cap layer is formed on the channel layer before the sacrificial layer is removed. This preliminary protective action ensures that when the sacrificial layer is subsequently etched away, the channel layer is already protected against dopant diffusion, preventing buckling and maintaining drive current.
2Productivity
If etching process is used to remove sacrificial layers, then channel members are released, but etch selectivity is lost leading to channel layer damage
Solution Approach 1:
The cap layer acts as an intermediary protective layer between the etching process and the channel layer. It provides etch selectivity by being more resistant to the etching chemistry used to remove the sacrificial layer, thereby protecting the channel layer from damage while still allowing complete removal of the sacrificial layer.
Solution Approach 2:
The etching process parameters are optimized to exploit the difference in etch resistance between the cap layer and the sacrificial layer. By controlling etch chemistry and conditions, the process selectively removes the sacrificial layer while the cap layer remains intact to protect the channel layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents dopant diffusion, maintains etch selectivity, and reduces defects, thereby enhancing the performance and reliability of MBC transistors by preserving the integrity of channel layers.
Implementation Method 1
at least one cap layer is disposed between each channel layer and an adjacent sacrificial layer
Implementation Method 2
maintains etch selectivity, and reduces defects, thereby enhancing the performance and reliability of MBC transistors
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.