Horizontal GAA Channel Doping for Defect-Free Threshold Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing transistor technologies face challenges in achieving high drive current and fast switching speeds while minimizing transistor size, particularly in horizontal gate-all-around (hGAA) devices, due to limitations in gate dielectric thickness and doping methods that can introduce defects or be costly and space-constrained.
Innovation Solution
A method for forming horizontal gate-all-around devices involves selectively etching a superlattice structure to create voids and doped semiconductor material layers between source and drain regions, using controlled doping processes to adjust threshold voltage and enhance electrostatic control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods (ion implantation or metal layer deposition) are used to adjust threshold voltage, then threshold voltage control is achieved, but channel defects are introduced or manufacturing cost and complexity increase
Solution Approach 1:
The patent introduces a sacrificial layer as an intermediary substance that enables controlled dopant diffusion into the channel. This sacrificial layer acts as a temporary mediator that facilitates the doping process without directly becoming part of the final device structure, thereby achieving threshold voltage control without introducing channel defects associated with conventional ion implantation or metal layer deposition methods
Solution Approach 2:
The patent replaces the mechanical/physical processes of ion implantation and metal layer deposition with a chemical diffusion process. Instead of physically implanting ions or depositing metal layers, the invention uses thermal diffusion where dopants naturally diffuse through the channel material at controlled temperatures, eliminating the mechanical damage and complexity associated with conventional doping methods
2Length of moving object
If gate dielectric thickness is reduced to accommodate device scaling, then transistor size is reduced, but space constraints limit further scaling
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around the channel in multiple dimensions. This dimensional change allows for continued scaling of transistor size by utilizing vertical and lateral wrapping of the gate, effectively adding spatial dimensions to the gate structure rather than simply reducing gate dielectric thickness in one dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables defect-free hGAA devices with improved electrostatic coupling and reduced parasitic capacitance, allowing for efficient adjustment of threshold voltage and enhanced performance without space constraints.
Implementation Method 1
A superlattice structure comprising a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs is selectively etched to remove each of the first layers or each of the second layers
Implementation Method 2
The plurality of semiconductor material layers are doped to form doped semiconductor material layers
Data Source
AI summary
Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a doped semiconductor material between source regions and drain regions of the device. The method includes doping semiconductor material layers between source regions and drain regions of an electronic device.