Fin Profile Control to Reduce Line Edge Roughness

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Solution Overview

Problem

The complexity of semiconductor manufacturing processes is increased by the scaling down of semiconductor devices, leading to issues such as increased channel resistance and performance degradation due to line edge roughness in fin structures, particularly in FinFETs, which affect current flow and device performance.

Innovation Solution

A method for fabricating fins with controlled profiles by patterning and etching semiconductor substrates to form fins with significantly wider bases than tops, reducing line edge roughness through lateral recessing and deposition of inter-layer dielectrics, thereby improving fin structure geometry and reducing channel resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fin structures are scaled down to increase storage capacity and processing speed, then device density and performance are improved, but line edge roughness increases causing channel resistance and performance degradation

Engineering Contradiction:

Improvestorage capacity and processing speedVSAvoidline edge roughness

Core Design Contradiction:

ProductivityVSManufacturing precision

Solution Approach 1:

The fin structure is divided into two distinct width portions: a first width at the bottom portion and a second width at the top portion. This segmentation allows each portion to be optimized independently, with the wider bottom providing structural stability and the narrower top reducing line edge roughness effects, thereby resolving the contradiction between scaling down for productivity and maintaining manufacturing precision.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The fin structure employs asymmetric geometry where the bottom width differs from the top width. This asymmetric design specifically addresses the line edge roughness problem by creating a profile where the wider base provides mechanical stability while the tapered top reduces the impact of edge variations, enabling continued scaling without proportional increases in roughness-related defects.

Inventive Principle:

Principle #4Asymmetry

2Ease of manufacture

If conventional fin structures with uniform width are used, then manufacturing process is simpler, but channel resistance increases due to line edge roughness effects

Engineering Contradiction:

Improvefin structure fabricationVSAvoiddevice performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

Different portions of the fin structure are given different widths tailored to their specific functional requirements. The bottom portion has a wider width for structural support and stress distribution, while the top portion has a narrower width to minimize line edge roughness impact on the channel. This local differentiation improves reliability without significantly complicating the overall manufacturing process.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS20250331235A1Fin with profile control

Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.