Hybrid Nanosheet and Fin Structure for Scaled CMOS Gate Control
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Solution Overview
Problem
Existing semiconductor integrated circuit (IC) technologies face challenges in scaling down device sizes while maintaining device performance and reducing fabrication costs, particularly in addressing device performance degradation and complexity associated with defects in field-effect transistors.
Innovation Solution
The fabrication of hybrid nanostructure and fin structure devices, specifically combining gate-all-around (GAA) and fin-like field-effect transistors (FinFETs), is achieved by alternating layers of semiconductor materials like silicon and silicon germanium, with selective etching and epitaxial growth processes to form nanowires or nanosheets, and integrating both structures within a single CMOS process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device sizes continue to decrease to increase functional density, then productivity and production efficiency improve, but device performance degradation and fabrication complexity increase
Solution Approach 1:
The device is segmented into distinct regions: a first region containing nanosheet transistor structures and a second region containing FinFET structures. This segmentation allows each region to be optimized for specific performance requirements while maintaining overall device functionality at scaled dimensions.
Solution Approach 2:
Different transistor structures are implemented in different regions of the device. The first region uses nanosheet structures with specific material compositions (e.g., Ge-Si alloys) while the second region uses FinFET structures, allowing local optimization of electrical characteristics for different functional requirements.
2Productivity
If device sizes continue to decrease to increase functional density, then productivity and production efficiency improve, but fabrication complexity increases
Solution Approach 1:
The fabrication process uses a unified CMOS-compatible methodology that can produce both nanosheet and FinFET structures using similar process steps (epitaxial growth, selective removal, patterning). This multi-functional approach reduces the need for entirely separate fabrication lines for different device types.
Solution Approach 2:
The semiconductor stack is formed with alternating layers of different materials (e.g., Ge-Si layers separated by SiGe sacrificial layers) in a predetermined sequence before final device formation. This preliminary structuring enables subsequent selective removal and patternning steps to create different device types from a single unified stack.
3Ease of manufacture
If conventional transistor structures are used at scaled dimensions, then manufacturing simplicity is maintained, but gate control and short-channel effects deteriorate
Solution Approach 1:
The invention transitions from planar 2D channel structures to three-dimensional structures (nanosheets and fins) that provide gate control from multiple directions. The nanosheet structures enable gate-all-around control, while FinFET structures provide triple-gate control, significantly improving electrostatic control at scaled dimensions.
Solution Approach 2:
The device employs composite material structures including alternating layers of Ge-Si semiconductor layers and SiGe sacrificial layers. These composite structures enable selective etching processes that create the desired three-dimensional channel geometries while maintaining crystallographic quality and lattice matching.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control, reduces OFF-state current, and mitigates short-channel effects, allowing for aggressive scaling while maintaining performance and reducing fabrication costs.
Implementation Method 1
depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material
Implementation Method 2
selective etching and epitaxial growth processes to form nanowires or nanosheets
Data Source
AI summary
A method includes depositing a semiconductor stack within a first region and a second region on a substrate, the semiconductor stack having alternating layers of a first type of semiconductor material and a second type of semiconductor material. The method further includes removing a portion of the semiconductor stack from the second region to form a trench and with an epitaxial growth process, filling the trench with the second type of semiconductor material. The method further includes patterning the semiconductor stack within the first region to form a nanostructure stack, patterning the second type of semiconductor material within the second region to form a fin structure, and forming a gate structure over both the nanostructure stack and the fin structure.