Self-Aligned Backside Wiring in Stacked FET Integrated Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit technologies face challenges in achieving compact, high-density, and high-quality semiconductor devices with efficient self-alignment and low-cost manufacturing, particularly in stacked transistor structures like CFETs.
Innovation Solution
A method involving the formation of a stack of field effect transistors with self-aligned trenches and holes, followed by metal deposition and isolation, creates a compact integrated circuit device with self-aligned backside wiring lines, reducing misalignment errors and enabling flexible production.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional planar semiconductor devices are used, then manufacturing is simpler, but area efficiency and power efficiency are reduced
Solution Approach 1:
The patent transitions from traditional planar (2D) semiconductor device architecture to a vertical (3D) stacked transistor structure. Multiple transistor layers are stacked vertically on top of each other, utilizing the third dimension to increase device density and area efficiency while maintaining manufacturability through adapted fabrication processes
2Area of moving object
If stacked transistor structures are used, then area efficiency improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements self-aligned fabrication processes where each subsequent layer is automatically positioned relative to previous layers using the structure itself as a reference. Etch holes are self-aligned to metal patterns, and metal patterns are self-aligned to transistor structures, eliminating the need for separate alignment steps and reducing precision requirements
Solution Approach 2:
The patent performs preliminary patterning and alignment准备工作 before final assembly. Templates and masks are prepared in advance with precise patterns that guide subsequent deposition and etching steps, ensuring accurate positioning of vertical structures before they are fully formed
3Adaptability or versatility
If multiple metal layers and trenches are used for wiring, then routing flexibility improves, but parasitic capacitances increase
Solution Approach 1:
The patent utilizes vertical stacking of metal layers and trenches in the third dimension to provide routing flexibility. Multiple metal interconnect layers are stacked vertically, allowing signals to be routed through different vertical levels, which reduces the need for long lateral traces and thereby reduces parasitic capacitance while maintaining routing adaptability
4Manufacturing precision
If self-alignment processes are implemented, then manufacturing precision improves, but process complexity increases
Solution Approach 1:
The patent employs self-aligned processes where the structure itself serves as the alignment reference. Etch holes are formed that automatically align with underlying metal patterns, and subsequent metal depositions automatically align with previous layers. This self-alignment mechanism achieves high precision while actually simplifying the overall process by eliminating separate alignment and repositioning steps
Data Source
AI summary
A method for forming an integrated circuit device, the method comprising: forming a stack of field effect transistors, FETs, comprising a bottom FET and a top FET; forming a first trench underneath the bottom FET; forming a first hole, between the first trench and a first source/drain region of the bottom FET; forming a second hole, between the first hole and a contact of a contact layer arranged above the top FET; performing a first metal deposition to fill the first hole; the second hole; and part of the first trench, with metal; recessing the metal deposited in the first metal deposition; forming an isolation layer below the recessed metal; performing a second metal deposition to fill the first trench with metal, thereby forming a first backside wiring line in the first trench.