Stacked Nanoribbon Dual Metal Gate With Sacrificial Plug Isolation
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Solution Overview
Problem
The integration of N-type and P-type transistors within a single stack in GAA devices is challenging due to difficulties in etching away the first workfunction metal from the top nanoribbon channels without affecting the bottom transistors, leading to increased spacing and fin height, which complicates shallow trench isolation and polysilicon processing.
Innovation Solution
A sacrificial plug material is used between the semiconductor channels of the top transistor before depositing the first workfunction metal, allowing for reduced etching time and spacing between the top and bottom transistors, enabling spacings of 50 nm or less.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the first workfunction metal is etched away from the top nanoribbon channels to enable dual metal gate, then the top transistor can have different workfunction metal, but the etching process affects the bottom transistors and requires increased spacing
Solution Approach 1:
The patent divides the transistor stack into distinct regions by introducing sacrificial plugs between the top and bottom transistors. These plugs segment the structure, allowing selective etching of the first workfunction metal from the top nanoribbon channels while protecting the bottom transistors. The segmentation enables independent processing of different transistor regions, resolving the contradiction between achieving dual workfunction metal and maintaining tight spacing.
Solution Approach 2:
The sacrificial plugs act as intermediary elements that facilitate the selective removal of the first workfunction metal. These plugs are positioned between the top and bottom transistors and serve as a mediator during the etching process, allowing the etch to access and remove the workfunction metal from the top channels without affecting the bottom transistors. The intermediary plugs enable the dual metal gate structure while maintaining the required spacing constraints.
2Adaptability or versatility
If increased spacing is used between top and bottom transistors to protect bottom transistors during etching, then dual metal gate can be achieved, but fin height increases and processing becomes more difficult
Solution Approach 1:
The sacrificial plugs segment the transistor stack, creating distinct processing zones. This segmentation allows the etching process to be localized to the top transistor region, preventing the need for increased overall spacing between transistors. By dividing the structure into separable units, the patent enables dual workfunction metal implementation without the processing complications that would arise from increased fin height and spacing.
3Productivity
If reduced etching time is used to remove first workfunction metal, then processing efficiency improves, but complete removal from top channels without affecting bottom transistors becomes difficult
Solution Approach 1:
The sacrificial plugs serve as intermediary protective elements that enable short etching times while maintaining manufacturing precision. During the rapid etching process, the plugs act as physical barriers that prevent the etch from reaching the bottom transistors. This intermediary protection allows the use of aggressive, time-efficient etching parameters without sacrificing the precision needed to selectively remove only the top workfunction metal.
Solution Approach 2:
The sacrificial plugs are deposited in advance, before the etching process, to establish protective barriers in position. This preliminary action prepares the structure for subsequent rapid etching by pre-positioning the elements that will control etch penetration depth. The pre-deposited plugs enable the high-speed etching process to achieve complete removal of the top workfunction metal without risking damage to the bottom transistors.
Data Source
AI summary
Embodiments disclosed herein include semiconductor devices and methods of making such devices. In an embodiment, the semiconductor device comprises a plurality of stacked semiconductor channels comprising first semiconductor channels and second semiconductor channels over the first semiconductor channels. In an embodiment a spacing is between the first semiconductor channels and the second semiconductor channels. The semiconductor device further comprises a gate dielectric surrounding individual ones of the semiconductor channels of the plurality of stacked semiconductor channels. In an embodiment, a first workfunction metal surrounds the first semiconductor channels, and a second workfunction metal surrounds the second semiconductor channels.