GAA Gate Structure With Isolation Protection During Replacement Gate
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Solution Overview
Problem
GAA transistors face issues with isolation features being excessively etched during the replacement gate process, leading to electrical shorts and increased parasitic capacitance due to substantial loss, which affects the integrity and performance of the device.
Innovation Solution
A protection layer is deposited over the isolation feature before forming the dummy gate stack, followed by the formation of inner spacer features to prevent excessive etching and protect the isolation feature, ensuring the integrity of the GAA transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the replacement gate process is used to form GAA transistors, then gate control is improved and device performance is enhanced, but the isolation feature is excessively etched leading to electrical shorts and increased parasitic capacitance
Solution Approach 1:
A protection layer is deposited over the isolation feature before the etching process begins. This preliminary protective measure prevents excessive etching of the isolation feature while allowing the replacement gate process to proceed, thereby maintaining both device performance and isolation feature integrity
Solution Approach 2:
The protection layer acts as an intermediary between the etching process and the isolation feature. It mediates the interaction by being selectively removed after serving its protective function, thus preventing electrical shorts and parasitic capacitance issues while allowing the gate structure to be properly formed
2Productivity
If the replacement gate process is used, then gate-channel coupling is increased, but substantial loss of isolation feature material occurs causing electrical shorts
Solution Approach 1:
The protection layer is deposited in advance before the etching process that forms the gate structure. This preliminary action prevents substantial material loss from the isolation feature while still allowing the gate-channel coupling to be established through the replacement gate process
Solution Approach 2:
The protection layer, which might seem like an additional complex step, actually converts the harmful excessive etching into a controlled process. By protecting the isolation feature during etching, it enables the replacement gate process to achieve good gate control without the harmful side effect of material loss
3Reliability
If the replacement gate process is used, then device performance is enhanced, but parasitic capacitance increases due to isolation feature loss
Solution Approach 1:
The protection layer is applied before the etching process to prevent isolation feature material loss. This preliminary protection maintains the isolation feature's integrity, thereby preventing the generation of parasitic capacitance while still allowing the enhanced device performance to be achieved through proper gate formation
Solution Approach 2:
The protection layer serves as an intermediary that prevents direct contact between the etching process and the isolation feature. This mediation prevents the isolation feature degradation that would otherwise lead to increased parasitic capacitance, while allowing the gate structure to be properly formed for optimal device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The protection layer effectively prevents excessive etching of the isolation feature, reducing electrical shorts and parasitic capacitance, thereby enhancing the reliability and performance of the GAA transistor.
Implementation Method 1
A protection layer is deposited over the isolation feature before forming the dummy gate stack, followed by the formation of inner spacer features to prevent excessive etching and protect the isolation feature
Data Source
AI summary
Semiconductor structures and processes for forming the same provided. A semiconductor structure according to the present disclosure includes an insolation feature, a first base fin and a second base fin extending through and rising above the isolation feature, a first active region disposed over the first base fin, a second active region disposed over the second base fin, a gate structure disposed over the first active region, the second active region, and the isolation feature, and a protection layer sandwiched between the gate structure and the isolation feature.