Nanosheet Stack Layout for Block-Level Power and Speed Tuning
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in the limited flexibility and reduced performance gains due to the uniform use of nanosheets across semiconductor devices, which affects power, performance, area, and cost (PPAC) metrics, particularly in applications like system-on-chip (SOC), central processing units (CPU), graphic processing units (GPU), and high-performance computing (HPC), as existing methods fail to tailor nanosheet configurations to meet specific design specifications.
Innovation Solution
The implementation of varying nanosheet numbers and widths across different functional blocks within a single semiconductor device, allowing for customized power consumption and performance adjustments by configuring nanosheet stacks to match the requirements of each functional block, such as using 1-3 nanosheets for lower power consumption and 4-5 nanosheets for higher performance applications, and employing a stepped substrate to create a planar structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If uniform nanosheet configurations are used across all functional blocks, then manufacturing simplicity is maintained, but device performance and power efficiency cannot be optimized for different applications
Solution Approach 1:
The patent applies local quality by configuring different numbers and widths of nanosheets in different functional blocks based on their specific performance requirements. For example, high-performance blocks use more nanosheets with larger widths, while low-power blocks use fewer nanosheets with smaller widths, allowing each region to have optimized characteristics tailored to its function.
Solution Approach 2:
The semiconductor device is segmented into multiple functional blocks, each with independently optimized nanosheet configurations. This segmentation allows the device to be divided into regions with different performance characteristics, enabling simultaneous optimization for power efficiency, speed, and area in different parts of the chip.
2Speed
If more nanosheets are used to increase current flow and performance, then speed improves, but power consumption increases
Solution Approach 1:
The patent implements dynamic configuration of nanosheet parameters, where the number and width of nanosheets are adjusted based on the performance requirements of each functional block. This dynamic approach allows the device to achieve high speed in performance-critical blocks while maintaining low power consumption in less demanding blocks, rather than using a static uniform configuration across the entire device.
Solution Approach 2:
The patent changes key parameters of the nanosheets including the number of nanosheets, width of nanosheets, and spacing between nanosheets to optimize the balance between speed and power consumption. By varying these parameters across different functional blocks, the device achieves high-speed operation where needed while reducing power consumption in other areas.
3Area of moving object
If feature sizes and spacing are decreased to increase device density, then area efficiency improves, but fabrication difficulty increases
Solution Approach 1:
The patent employs parameter changes in the nanosheet configuration, specifically adjusting the width and spacing of nanosheets, to achieve high device density while maintaining manufacturability. By optimizing these parameters, the device achieves increased area efficiency without pushing the fabrication process beyond practical limits.
Data Source
AI summary
A method of making a semiconductor device includes determining a number of nanosheet regions. The method includes repeating processes of: recessing a surface of a semiconductor substrate relative to a top surface of the semiconductor substrate by a recess distance; depositing a layer of a first material; depositing a layer of a second material on the layer of the first material; removing a first portion of the layers of the first material and the second material while retaining a second portion of the layer of the first material and the layer of the second material; until the number of nanosheet regions is reached. The method includes forming a nanosheet stack on each of the plurality of nanosheet regions, wherein a first height of a first nanosheet stack on a first nanosheet region is different from a second height of a second nanosheet stack on a second nanosheet region.