Metal Oxide Gate Stack Formation for Reliable GAA Nanostructures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of forming reliable semiconductor devices at smaller sizes is exacerbated by the complexity of fabrication processes as feature sizes continue to decrease, making it difficult to achieve efficient and reliable manufacturing.
Innovation Solution
A method involving the formation of semiconductor devices with a gate containing a metal oxide layer using an oxidation process, utilizing multi-patterning and self-aligned processes to create fin structures and gate all around transistor structures with precise pitch control, and incorporating epitaxial growth and selective etching to form reliable channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and manufacturing difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple discrete stages including forming mandrels with first pitch, performing first self-aligned spacer formation, selective removal, second self-aligned spacer formation, and selective removal to create fins with second pitch. This segmentation allows complex multi-patterning to be achieved through manageable sequential steps, resolving the contradiction between scaling down feature sizes and maintaining process feasibility
Solution Approach 2:
Mandrels are formed in advance with a first pitch that is larger than the final desired fin pitch. These preliminary structures serve as templates for subsequent spacer formation and selective removal processes. The preliminary action of creating these sacrificial mandrels enables precise control over the final fin dimensions and spacing, allowing scaling to smaller features while maintaining manufacturing reliability
2Area of stationary object
If feature sizes decrease to increase functional density, then chip area utilization is improved, but reliability of device formation becomes more difficult to achieve
Solution Approach 1:
Self-aligned spacers are formed using the mandrels and previously formed structures as alignment references. The spacers automatically position themselves relative to the mandrels without requiring additional alignment steps, ensuring precise pitch control and reducing variability. This self-alignment mechanism maintains high device formation reliability even as feature sizes decrease and functional density increases
Solution Approach 2:
The process transforms the pitch parameter from the first pitch of mandrels to the second pitch of fins through controlled spacer formation and selective removal. By changing the structural parameters (from mandrel pitch to fin pitch) through intermediate spacer layers, the process achieves smaller feature dimensions while maintaining precise control over final dimensions, thereby preserving reliability during scaling
3Manufacturing precision
If multi-patterning and self-aligned processes are used to create precise pitch control, then manufacturing precision is improved, but device complexity and process steps increase
Solution Approach 1:
The fabrication process embeds multiple levels of patterning within each other: first mandrels are formed, then first spacers are formed around them, followed by selective removal, then second spacers are formed, and finally selective removal to create fins. Each stage nests within the previous stage's structures, allowing precise pitch control to be achieved through hierarchical self-aligned processes without requiring completely separate fabrication sequences
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable semiconductor devices with improved reliability and operation speed by reducing parasitic capacitance and ensuring precise feature formation, enhancing manufacturing efficiency and device performance.
Implementation Method 1
forming a gate all around transistor structure with a released semiconductor nanostructure embedded within the gate all around transistor structure
Implementation Method 2
incorporating epitaxial growth and selective etching to form reliable channel structures
Data Source
AI summary
A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.