Nano-FET Source/Drain Epitaxy With (110) Nanostructures
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in integrating electronic components efficiently while maintaining high performance, particularly in nano-FETs, due to issues with current flow and epitaxial growth.
Innovation Solution
The formation of semiconductor layers with specific crystallographic orientations, such as (110), followed by patterning into multi-layer stacks and nanostructures, enhances current flow and allows for efficient epitaxial source/drain regions, utilizing insulating fins to prevent coalescence and improve device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but additional problems arise with current flow and epitaxial growth
Solution Approach 1:
The patent changes the crystallographic orientation parameter of the semiconductor layer from conventional orientations to (110) orientation. This parameter change fundamentally alters the material properties, enabling higher hole mobility and improved current flow characteristics while maintaining the scaled dimensions, thus resolving the contradiction between integration density and current flow performance
Solution Approach 2:
The patent employs a composite structure consisting of alternating semiconductor layers with different materials and crystallographic orientations. This multi-layer composite approach allows optimization of current flow in specific directions while maintaining overall device scalability, addressing both integration density and performance requirements
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but epitaxial growth becomes problematic
Solution Approach 1:
The patent changes the crystallographic orientation parameter to (110), which fundamentally improves epitaxial growth characteristics. This orientation enables better atomic layer formation and reduces defects during the epitaxial process, making manufacturing feasible even at reduced feature sizes required for high integration density
Solution Approach 2:
The patent performs preliminary patterning to form multi-layer stacks with specific orientations before performing the epitaxial growth step. This preliminary structuring ensures that the epitaxial growth occurs on properly prepared surfaces with correct crystallographic alignment, facilitating successful growth at scaled dimensions
3Reliability
If semiconductor layers are patterned into multi-layer stacks to improve current flow, then hole mobility increases, but device structure becomes more complex
Solution Approach 1:
The patent segments the semiconductor structure into multiple thin layers with alternating orientations, where each layer contributes to the overall current flow in a specific direction. This segmentation allows optimization of hole mobility through controlled carrier transport in each layer while maintaining a systematic fabrication approach
Solution Approach 2:
The multi-layer stack structure serves multiple functions simultaneously: it provides current flow pathways, enables self-aligned patterning, and facilitates epitaxial growth. This multi-functionality reduces the need for separate processing steps, offsetting the structural complexity with process integration benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves current flow and device performance by aligning semiconductor layers with (110) orientation, enabling higher hole mobility and efficient epitaxial growth, thus enhancing the integration density and functionality of nano-FETs.
Implementation Method 1
The formation of semiconductor layers with specific crystallographic orientations, such as (110), followed by patterning into multi-layer stacks and nanostructures, enhances current flow and allows for efficient epitaxial source/drain regions
Implementation Method 2
efficient epitaxial source/drain regions, utilizing insulating fins to prevent coalescence and improve device performance
Data Source
AI summary
A method includes forming a first nanostructure and a second nanostructure over a semiconductor fin; forming a recess in the first nanostructure, the second nanostructure, and the semiconductor fin; epitaxially growing a first layer in the recess, a first portion of the first layer being disposed along a first sidewall of the first nanostructure, a second portion of the first layer being disposed along the semiconductor fin, the first portion of the first layer comprising two sidewalls extending toward a middle of the recess, the first portion of the first layer further comprising a first surface most distal from the first sidewall, the first portion being physically separated from the second portion; and epitaxially growing a second layer over and forming a physical connection between the first portion of the first layer and the second portion of the first layer.