Semiconductor Interconnect Structure With Selective Etch-Resistant Layer
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to improve integration density and reduce contact resistance while minimizing reliability issues such as time-dependent dielectric breakdown, electromigration, and stress migration in interconnect structures.
Innovation Solution
The implementation of a self-aligned etch-resistant layer and capping material in interconnect structures, which includes forming conductive features with an inhibitor material to prevent the etch-resistant layer from depositing on conductive features, enhancing contact area and reducing contact resistance, and using an etch stop layer to protect the dielectric layer from damage during etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etch-resistant layer is deposited over the conductive features to protect them during etching, then the dielectric layer is protected from damage, but the contact area between conductive features is reduced and contact resistance increases
Solution Approach 1:
The patent applies different properties to different regions: the etch-resistant layer is selectively deposited only on the dielectric layer surface, not on the conductive features. This is achieved through selective deposition processes that prevent etch-resistant material from accumulating on conductive features, thereby maintaining good electrical contact while still protecting the dielectric layer where needed.
Solution Approach 2:
The patent introduces an inhibitor material as an intermediary layer between the conductive features and the etch-resistant layer. This inhibitor material prevents the etch-resistant layer from depositing on the conductive features, ensuring that the conductive features remain exposed for proper electrical contact while the dielectric layer receives the protective etch-resistant coating.
2Productivity
If the integration density is improved by reducing minimum feature size, then more components can be integrated into a given area, but the contact resistance increases and reliability issues arise
Solution Approach 1:
The patent changes the deposition parameters and selectivity of the etch-resistant layer formation process to achieve different outcomes on different surfaces. By controlling deposition conditions, the process achieves minimal or zero coverage on conductive features while providing adequate coverage on the dielectric layer, thus maintaining low contact resistance even as feature sizes are reduced for higher integration density.
3Reliability
If the etch-resistant layer is made thicker to better protect the dielectric layer, then protection against damage is improved, but leakage increases and device performance deteriorates
Solution Approach 1:
The etch-resistant layer thickness is optimized locally: thicker regions are formed only where dielectric layer protection is needed, while regions adjacent to conductive features maintain minimal or zero thickness. This spatial variation in thickness prevents leakage paths while providing adequate protection where required, resolving the contradiction between protection and leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves device performance by reducing leakage and contact resistance, preventing reliability issues, and minimizing RC delay, thereby enhancing the overall functionality of semiconductor devices.
Implementation Method 1
an etch-resistant layer is selectively deposited over the first dielectric layer, without being deposited on the first conductive features
Implementation Method 2
An inhibitor material may optionally be selectively deposited over the first conductive features, without being deposited on the first dielectric layer
Implementation Method 3
A capping material is selectively deposited over the first conductive features, without being deposited on the first dielectric layer or the etch-resistant layer
Implementation Method 4
An etch stop layer is deposited over the etch-resistant layer and the capping material
Data Source
AI summary
An improved method of forming conductive features and a semiconductor device formed by the same are disclosed. In an embodiment, a method includes providing a first conductive feature in a first dielectric layer; selectively depositing an etch-resistant layer over the first dielectric layer, a sidewall of the etch-resistant layer being coterminous with a sidewall of the first dielectric layer; after selectively depositing the etch-resistant layer, selectively depositing a capping layer over the first conductive feature adjacent the etch-resistant layer, a sidewall of the capping layer being coterminous with a sidewall of the first conductive feature; and forming a second conductive feature over the capping layer, the etch-resistant layer separating the second conductive feature from the first dielectric layer.