GAA Fin Structure With Dielectric Isolation for Leakage Control
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Solution Overview
Problem
Existing gate-all-around (GAA) FETs face challenges with leakage current and parasitic PN junctions due to the lack of control over the bottom part of the channel region, which affects the ION/IOFF ratio.
Innovation Solution
Incorporating an insulating layer between the bottommost gate structure and the underlying semiconductor substrate, reducing leakage current and minimizing parasitic PN junctions by forming a gate structure that surrounds the channel region on all sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate structure surrounds the channel region on all sides (GAA FET), then fuller depletion and reduced short-channel effects are achieved, but leakage current and parasitic PN junctions increase due to lack of control over the bottom part of the channel region
Solution Approach 1:
An insulating layer is introduced as an intermediary between the bottommost gate structure and the underlying semiconductor substrate. This insulating layer acts as a mediator that electrically isolates the gate structure from the substrate, preventing the formation of parasitic PN junctions and reducing leakage current while maintaining the beneficial all-around gate control.
Solution Approach 2:
The gate structure is segmented into multiple gates stacked vertically, with insulating layers positioned between adjacent gates and between the bottommost gate and the substrate. This segmentation allows each gate to independently control different portions of the channel region, providing fuller depletion while the insulating layers prevent harmful electrical interactions with the substrate.
2Productivity
If transistor dimensions are scaled down to nanometer technology process nodes, then device density and performance are improved, but fabrication and design challenges increase
Solution Approach 1:
The invention transitions from planar (2D) gate control to three-dimensional (3D) gate-all-around control by stacking multiple gates vertically. This dimensional change enables fuller depletion of the channel region and better electrostatic control at nanometer scales, addressing the fabrication and design challenges associated with continued scaling.
Solution Approach 2:
Multiple gate structures are nested vertically one above another, with insulating layers positioned between them. This nested configuration allows compact vertical stacking that achieves full channel control while managing the complexity of nanometer-scale fabrication through a systematic layered architecture.
3Ease of manufacture
If the bottom part of the channel region is not under gate control (FinFET), then fabrication is simpler, but leakage current increases and ION/IOFF ratio deteriorates
Solution Approach 1:
The gate control is segmented into multiple discrete gate structures stacked vertically, with the bottommost gate positioned close to the channel region. This segmentation enables complete wrap-around control of the channel, including the bottom portion, thereby reducing leakage current and improving the ION/IOFF ratio while maintaining manufacturability through standardized stacking processes.
Solution Approach 2:
Insulating layers serve as intermediaries that electrically isolate each gate structure from the substrate and from adjacent gates. This intermediary approach enables full gate control over the channel region including the bottom part, while preventing direct electrical contact that would create parasitic junctions and leakage paths.
Data Source
AI summary
An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substrate.